Abstract. This paper presents design details for a bit-level systolic cell that has been recently introduced for implementing digital signal processing (DSP) operations over finite rings. This paper concentrates on the efficient construction of the basic cell, using a 3/z p-well CMOS technology. The design uses a 5-bit, 32-word dynamic ROM as the main computational element, and details of all elements of the cell are discussed with regard to minimizing the (Area.Period) product. The final cell design and simulation details are compared with a pipelined gated full-adder, designed in the same technology, which represents the most common type of binary bit-level systolic cell.It is shown that the (Area.Period) product of the binary cell is 68% greater than that of the finite ring cell, but the power of the finite ring cell, in implementing fixed coefficient inner product multiplications, is much greater than that of the binary cell. There are also advantages associated with the reduction of the connectivity across the dynamic range, including clock-skew reduction, ease of testing, and fault detection. The conclusion is that in certain classes of DSP operations, this new cell can offer more than an order of magnitude improvement in (Area.Period) product of complete bit-level systolic arrays, over its binary counterpart.

Hardware-in-the-Loop Technology and Simulation GroupAbstract-This paper presents the design of the Digital RF Processing (DRFP) system for generating many of the RF effects within the Advanced Radar Environment Simulator (ARES) Hardware-in-the-Loop system developed within the Hardwarein-the-Loop Technology and Simulation Group (HTS) of Weapons Systems Division (WSD), DSTO. This system is based on Digital RF Memory (DRFM) technology. The DRFM signal processing is performed on a digitised signal on a commercialoff-the-shelf (COTS) Field Programmable Gate Array (FPGA) hardware board. The RF Up/Down conversion is performed by a COTS RF module. The RF up/down converter translates an 800MHz instantaneous band in range 2-18 GHz down to 500 MHz IF signal (100 -900 MHz). The ARES Digital RF Processor (DRFP) provides the technique designer with a set of tools to model a number of environmental effects, such as Doppler, Range Delay, intra-pulse complex modulations, and multi-point convolutions. The ARES DRFP provides a real-time communication link to receive high fidelity generic environmental parameters which are computed by a numerical model of the radar environment. This feature provides the technique designer with significant flexibility compared to other typical Radar/RF scene generators. This paper discusses the implementation details and the design strategies of the development. Preliminary results of the ARES DRFP output are also discussed.