We present a 46nm 6F 2 buried word-line (bWL) DRAM technology, enabling the smallest cell size of 0.013um2 published to date. The TiN/ W buried word-line is built below the Si surface, forming a low resistive interconnect and the metal gate of the array transistors. We demonstrate high array device on-current, small parameter variability, high reliability and small parasitic capacitances, resulting in an excellent array performance. The array device can be scaled down to 30nm without compromising its performance.

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