6F&lt;sup&gt;2&lt;/sup&gt; buried wordline DRAM cell for 40nm and beyond

Schloesser, T.; Jakubowski, Frank; Kluge, Johannes von; Graham, Andrew; Slesazeck, Stefan; Popp, M.; Baars, P.; Muemmler, K.; Moll, P.; Wilson, K.; Buerke, A.; Koehler, D.; Radecker, J.; Erben, Elke; Zimmermann, Uwe; Vorrath, T.; Fischer, B.; Aichmayr, G.; Agaiby, Rimoon; Pamler, W.; Schuster, Thomas J; Bergner, W.; Mueller, Wolfgang

doi:10.1109/iedm.2008.4796820

Cited by 33 publications

(15 citation statements)

References 1 publication

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“…None of these works show the impact of bitline coupling on retention time. In addition, [30] and [2] studied only DRAMs with a folded bitline architecture, while modern DRAMs use an open bitline architecture [22,24,32,33]. Open bitline architectures permit the use of smaller DRAM cells, improving DRAM density, but suffer from increased bitline-bitline coupling noise [33].…”

Section: Data Pattern Dependencementioning

confidence: 98%

An experimental study of data retention behavior in modern DRAM devices

LiuJamie

JaiyenBen

KimYoongu

et al. 2013

SIGARCH Comput. Archit. News

179

403

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DRAM cells store data in the form of charge on a capacitor. This charge leaks off over time, eventually causing data to be lost. To prevent this data loss from occurring, DRAM cells must be periodically refreshed. Unfortunately, DRAM refresh operations waste energy and also degrade system performance by interfering with memory requests. These problems are expected to worsen as DRAM density increases.The amount of time that a DRAM cell can safely retain data without being refreshed is called the cell's retention time. In current systems, all DRAM cells are refreshed at the rate required to guarantee the integrity of the cell with the shortest retention time, resulting in unnecessary refreshes for cells with longer retention times. Prior work has proposed to reduce unnecessary refreshes by exploiting differences in retention time among DRAM cells; however, such mechanisms require knowledge of each cell's retention time.In this paper, we present a comprehensive quantitative study of retention behavior in modern DRAMs. Using a temperaturecontrolled FPGA-based testing platform, we collect retention time information from 248 commodity DDR3 DRAM chips from five major DRAM vendors. We observe two significant phenomena: data pattern dependence, where the retention time of each DRAM cell is significantly affected by the data stored in other DRAM cells, and variable retention time, where the retention time of some DRAM cells changes unpredictably over time. We discuss possible physical explanations for these phenomena, how their magnitude may be affected by DRAM technology scaling, and their ramifications for DRAM retention time profiling mechanisms.

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Section: Data Pattern Dependencementioning

confidence: 98%

An experimental study of data retention behavior in modern DRAM devices

LiuJamie

JaiyenBen

KimYoongu

et al. 2013

SIGARCH Comput. Archit. News

179

403

View full text Add to dashboard Cite

show abstract

“…We modeled the memory cell architecture (of 6F 2 area), the equalization circuit, the wordline driver, and the sense amplifier using the designs suggested in [18], [25] and [26]. The baseline DRAM configuration targets a 1Gb DDR3-1066 (533MHz) x8 memory with core timings of 7-7-7 cc (refer Section 4.1) at 45nm.…”

Section: Dram Cross-section Spice Simulationsmentioning

confidence: 99%

Towards variation-aware system-level power estimation of DRAMs

Chandrasekar

Weis

Åkesson

et al. 2013

Proceedings of the 50th Annual Design Automation Conference

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DRAM vendors provide pessimistic current measures in memory datasheets to account for worst-case impact of process variations and to improve their production yield, leading to unrealistic power consumption estimates. In this paper, we first demonstrate the possible effects of process variations on DRAM performance and power consumption by performing Monte-Carlo simulations on a detailed DRAM cross-section. We then propose a methodology to empirically determine the actual impact for any given DRAM memory by assessing its performance characteristics during the DRAM calibration phase at system boot-time, thereby enabling its optimal use at run-time. We further employ our analysis on Micron's 2Gb DDR3-1600-x16 memory and show considerable over-estimation in the datasheet measures and the energy estimates (up to 28%), by using realistic current measures for a set of MediaBench applications.

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“…The access transistor of an STT-MRAM cell may be 56 times larger than that of the magnetic storage element [20], and 9 times larger than the entire DRAM cell [13]. To alleviate this effect, a crosspoint architecture was proposed [20], which amortizes the cost of large access transistors by sharing them among a number of storage elements.…”

Section: Introductionmentioning

confidence: 99%

Low write-energy STT-MRAMs using FinFET-based access transistors

Shafaei

Wang

Pedram

2014

2014 IEEE 32nd International Conference on Computer Design (ICCD)

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Spin-Transfer Torque Magnetic RAM (STT-MRAM) technology requires a high current in order to write data into memory cells, which gives rise to large access transistors in conventional MOS-accessed cells. On the other hand, FinFET devices offer higher ON current and denser layout compared with planar CMOS transistors. This paper thus proposes the design of an energy-efficient STT-MRAM cell which utilizes a FinFET access transistor. To assess the performance of the new cell, optimal layout-related parameters of the FinFET access transistor and the MTJ are analytically derived in order to minimize the STT-MRAM cell area. Afterwards, detailed cell-and architecture-level comparisons between FinFET-vs. MOS-accessed STT-MRAMs are performed. According to the comparison results, while the area of the MOS-accessed STT-MRAM increases significantly under 3ns write pulse width (τ w ), the FinFET-based design can effectively function under τw = 2ns, at the cost of slight increase in the memory area. Hence, the FinFET-accessed STT-MRAM offers denser area and higher energy efficiency compared with the conventional MOS-accessed counterpart.

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6F<sup>2</sup> buried wordline DRAM cell for 40nm and beyond

Cited by 33 publications

References 1 publication

An experimental study of data retention behavior in modern DRAM devices

An experimental study of data retention behavior in modern DRAM devices

Towards variation-aware system-level power estimation of DRAMs

Low write-energy STT-MRAMs using FinFET-based access transistors

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