Abstract

The long-term survival of a business often hinges upon its ability to successfully introduce new products into the market place.

PurposeAlthough small- and medium-sized enterprises (SMEs) play major roles in most economies in terms of job creation, innovation and contribution to national income, they are often underrepresented in public procurement markets. This paper aims to explore how the dynamic capabilities theory can improve SME participation in public procurement.Design/methodology/approachThrough a systematic literature review, the paper identifies common barriers to the effective participation of SMEs in public procurement and explores the applicability of the dynamic capabilities theory in addressing these barriers.FindingsA theoretical analysis was conducted to identify possible relationships between the factors reported in the literature as barriers to SME participation in public procurement and different components of the dynamic capabilities of firms (i.e. sensing, seizing, reconfiguring and learning). Seven key propositions were generated to guide future research.Research limitations/implicationsDespite its contributions, this paper is based solely on a systematic literature review and theoretical analysis. Future studies could use meta-analysis to review multiple studies relating to the nexus between SMEs and public procurement, hence improving methodological rigour.Practical implicationsThe paper contributes to the ongoing debate about whether and how SMEs can leverage their resources and capabilities to develop self-help strategies to improve participation in public procurement, an area yet underexplored in the literature.Originality/valueThis is one of the few studies examining the implications of firm-level capabilities of SME activity in public procurement markets. The findings may be beneficial to SME managers/owners, particularly regarding firms' ability to leverage resources and capabilities to participate effectively in public procurement.

Purpose -The purpose of this paper is to review some of the learning technologies associated with teaching and learning in Higher Education (HE). It looks at Elearning and Information Technology (IT) as tools for replacing the traditional learning experience in HE, i.e. the 'chalk and talk' lecture and seminar. HE is on the threshold of being transformed through the application of learning technologies. Are we on the brink of a new way of learning in HE after a tried and tested formula over eight hundred years? Design/methodology/approach -Adopting a case based approach, the fieldwork for this research took place at two UK Higher Education Institutes (HEI's). A number of units that included IT based learning were identified. All units included a web site that was aimed at supporting students' learning. The data was collected through unstructured discussion with the lecturer and a questionnaire to students. Findings -This paper considers and highlights the key findings from the sample linking them to the literature with the purpose of testing the aim/title of this paper. Evidence suggested the implications for HEI's are they cannot assume that presenting new technologies automatically makes their institutions "youth friendly"; this new generation would like to see some concrete benefits of technology. Originality/value -From this small-scale investigation this paper attempts to investigate which direction the threshold may go. There has been eight hundred years of learning in the UK, is this generation wanting a new chapter. Evidence from this research suggests not, it will only play a bit part. They can help free up time in order to engage and support students in new and interesting ways.

This paper introduces a real-time connected component labelling algorithm designed for Field Programmable Gate Array (FPGA) implementation. The algorithm run-length encodes the image, and performs connected component analysis on this representation. The run-length encoding, together with other parts of the algorithm, is performed in parallel; sequential operations are minimized as the number of runs is typically far less than the number of pixels. The architecture is designed mainly on Block RAM (i.e.internal RAM) of the FPGA. A comparison with the multi-pass algorithm in hardware and software is presented to show the advantages of the algorithm. The algorithm runs comfortably in real-time with reasonably low resource utilization, making integration with other real-time algorithms feasible