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G.Keane@ee.qub.ac.uk J.R.Spanier@ee.qub.ac.uk R.Woods@ee.qub.ac.uk 1. ABSTRACT Adders and multipliers are key operations in DSP systems. The power consumption of adders is well understood but there are few detailed results on the choice of multipliers available. This paper considers how the power consumption of a number of multiplier structures such as Carry-Save array and Wallace Tree multipliers varies with data wordlengths and different layout strategies. In all cases, results were obtained from EPIC PowerMill™ simulations of actual synthesised circuit layouts. Analysis of the results highlights the effects of routing and interconnect optimization for low power operation and gives clear indications on choice of multiplier structure and design flow for the rapid design of DSP systems.

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The paper presents the development of a low-power synthesis flow for the development of dedicated silicon circuits fbr data-dominated applications such as DSP systems. The work was carried out as part of a European ESPRIT low power action and a collaborative "low-power" project involving the universities of Liverpool, Manchester and Sheffield The design flow is briefly d e s m i and some results are presented for mult~~lier implementations and their use m the development of a Discrete Cosine Transform (DCT) circuit