Low-Power Custom Regular Processor Synthesis Flow

Woods, Roger; Lightbody, Gordon; Spanier, Jonathan Robert; Keane, G.

doi:10.1007/978-1-4757-3182-8_5

Cited by 1 publication

(1 citation statement)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…High level design methodologies to detect switching activity of various components to facilitate switch-off can therefore have considerable impact on static power which is now becoming the dominant feature. Thus an architectural design methodology to address both performance and energy considerations from a system level is vital [36].…”

Section: Future Challengesmentioning

confidence: 99%

From Bit Level Systolic Arrays to HDTV Processor Chips

Woods¹,

McCanny²,

McWhirter

2007

J Sign Process Syst Sign Image Video Technol

View full text Add to dashboard Cite

The initial part of this paper reviews the early challenges (c 1980) in achieving real-time silicon implementations of DSP computations. In particular, it discusses research on application specific architectures, including bit level systolic circuits that led to important advances in achieving the DSP performance levels then required. These were many orders of magnitude greater than those achievable using programmable (including early DSP) processors, and were demonstrated through the design of commercial digital correlator and digital filter chips. As is discussed, an important challenge was the application of these concepts to recursive computations as occur, for example, in Infinite Impulse Response (IIR) filters. An important breakthrough was to show how fine grained pipelining can be used if arithmetic is performed most significant bit (msb) first. This can be achieved using redundant number systems, including carry-save arithmetic. This research and its practical benefits were again demonstrated through a number of novel IIR filter chip designs which at the time, exhibited performance much greater than previous solutions. The architectural insights gained coupled with the regular nature of many DSP and video processing computations also provided the foundation for new methods for the rapid design and synthesis of complex DSP System-on-Chip (SoC), Intellectual Property (IP) cores. This included the creation of a wide portfolio of commercial SoC video compression cores (MPEG2, MPEG4, H.264) for very high performance applications ranging from cell phones to High Definition TV (HDTV). The work provided the foundation for systematic methodologies, tools and design flows including high-level design optimizations based on^algorithmic engineering^and also led to the creation of the Abhainn tool environment for the design of complex heterogeneous DSP platforms comprising processors and multiple FPGAs. The paper concludes with a discussion of the problems faced by designers in developing complex DSP systems using current SoC technology.

show abstract

Section: Future Challengesmentioning

confidence: 99%