This paper presents an experimental platform for regulating the DC motor angular speed powered by photovoltaic cells. The experimental platform comprises an Eco Green Energy EGE-260P-60 solar panel, DC/DC SEPIC converter, DC bus, DC/DC buck converter, DC motor and Nexys 4 board with an Artix-7 100T FPGA. The DC/DC SEPIC converter is used for harvesting the maximum amount of energy from the PV cells using the perturb and observe algorithm to track the maximum power point. The DC/DC buck converter is used as the motor drive using the active disturbance rejection control to regulate the angular speed of the DC motor. In addition, the FPGA architecture design is presented using a hierarchical top-down methodology with the VHDL hardware description language and Xilinx System Generator tool. The software takes advantage of the FPGA’s concurrency to simultaneously evaluate the different processes, which is the main reason for choosing this digital device. Several tests were performed on the platform such as irradiance changes, DC bus variations, DC motor connection and load torque variations applied in the motor shaft. The results indicate that the maximum power is obtained from the photovoltaic cells, establishing the minimum operating conditions. In addition, the control approach estimates and cancels the effects of disturbances caused by variations in the environmental conditions, photovoltaic system, DC bus, and load changes in order to regulate DC motor speed.
Este trabajo presenta el diseño e implementación de un controlador robusto para el seguimiento de velocidad de un motor síncrono de imanes permanentes (MSIP). Se propone un controlador lineal basado en la retroalimentación dinámica de la salida pasiva estática del error exacto. El controlador pasivo propuesto requiere del conocimiento del par de carga, por lo que el mismo es estimado con un observador tradicional de orden reducido. El MSIP es impulsado por medio de un inversor multinivel trifásico de celdas en cascada de cinco niveles. Para la implementación del controlador, estimador y modulador multinivel se emplea un arreglo de compuertas programable en campo (FPGA) de la familia Spartan-6 XC6SLX9. El procesamiento en paralelo que provee este dispositivo permite obtener un tiempo de muestreo de 10 us. Los resultados de simulación y experimentales muestran que el controlador propuesto tiene un excelente desempeño.
This paper deals with the design and implementation of the conventional Level‐Shifted‐PWM (LS‐PWM) and the PWM‐hybrid modulation techniques in a Field‐Programmable Gate Array (FPGA) development card, applicable to binary asymmetric multilevel converters; particularly herein, the Binary‐Asymmetric Cascade Multilevel Inverter is treated (B‐ACMLI). We employ an FPGA‐based switching‐controller to provide pulses for Multilevel Inverter (MLI) power semiconductors via their gate‐drivers. The modulation strategies were implemented via an FPGA with a 32‐bit floating‐point architecture considering the IEEE‐754 standard's recommendations. The portability of the design is ensured using VHDL . The use of embedded RAM blocks minimizes the logical resources consumed into the FPGA, increases overall speed, and reduces power consumption. A comparison is presented in terms of the number of resources used in both modulation techniques. A low‐cost FPGA board named Pipistrello is used. Pipistrello is an FPGA development board for Xilinx Spartan‐6 LX45, designed by Saanlima Electronics. The platform consisting of a single‐phase seven‐level inverter B‐ACMLI hardware prototype. The experimental results show the effectiveness of the approach. As isolated voltage‐sources, photovoltaic modules are used for the experimental setup to the B‐ACMLI.
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