Abstract

In the paper a method for estimation the circuit testability on the Register Transfer Level (RTL) is presented. The method allows to perform fast testability estimation in linear time complexity (regarding the number of components and interconnects of the circuit). Proposed approach is based on utilization of controllability and observability measurement for estimation of overall circuit testability. The application of developed method is demonstrated in a software tool for the development of RTL benchmark circuits with predefined testability properties. The resultsgained by our testability analysis method are compared with the results of professional ATPG tool. Experiments show the good correlation of the results obtained by our method and professional ATPG tool with significantly lower time complexity when our algorithm is used.

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Major drawback of high level design methodologies such as RTL can be seen in the following facts. First, they lack of sufficiently precise fault models -compared to sophisticated models available for low level description levels such as logic gate level. Second, since the structure of a design changes significantly with every logic synthesis run, testability analysis is typically performed only after final logic synthesis. As a consequence, results of the analysis could be obtained when it is very costly to reflect them in the high level design. The drawbacks can be removed in several ways. In the contribution, it is supposed the analysis is performed at RTL and is efficient enough to be run after each change in RTL design -giving a designer an immediate information about the change impact to testability parameters. Under the assumption, low computational complexity and accuracy are the requirements posed to the analysis. The latter requirement is met if strong correlation is detected between RTL testability analysis results and lowlevel test pattern generation results. In the paper, it is shown such a correlation exists although relatively simple academic RTL testability analysis solution is compared to widely used commercial gate-level test pattern generation solution. Detail results achieved during the experiments over scan circuits are presented, discussed and summarized in the paper.