Testability improvements based on the combination of analytical and evolutionary approaches at RT level

Strnadel, Josef; Kotásek, Zdenĕk

doi:10.1109/dsd.2002.1115365

Cited by 5 publications

(2 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It allows to verify testability of any RT-level circuit structure modified using any DfT method -e.g. methods [2], [3], [6], [10], [11].…”

Section: Discussionmentioning

confidence: 99%

Testable design verification using Petri nets

Růžička

2003

Euromicro Symposium on Digital System Design, 2003. Proceedings.

View full text Add to dashboard Cite

In the paper, a method for formal verification of testable design is presented. As a input, a digital circuit structure at RT level designed using any DfT technique is assumed. Proposed method enables to verify testability of each element or a part of the circuit. Petri Net based model and common methods of Petri Net analysis are utilised. On the model, it is possible to prove, if a circuit element or a part of the circuit under test can be tested by a selected way -if paths, chosen for diagnostic data transport, are passable or not and if not, for what reason.

show abstract

“…It allows to verify testability of any RT-level circuit structure modified using any DfT method -e.g. methods [2], [3], [6], [10], [11].…”

Section: Discussionmentioning

confidence: 99%

Testable design verification using Petri nets

Růžička

2003

Euromicro Symposium on Digital System Design, 2003. Proceedings.

View full text Add to dashboard Cite

show abstract

“…It is different from other approaches which evaluate the testability measures, reachability metrics are the results of such methodologies [9,10,11].…”

Section: The Model Of Control and Transparency Propertiesmentioning

confidence: 99%

Formal approach to synthesis of a test controller

Růžička

Tupec

Proceedings. 11th IEEE International Conference and Workshop on the Engineering of Computer-Based Systems, 2004.

View full text Add to dashboard Cite

In the paper, a method for formal construction of a test controller of the RT level digital circuit is presented. As input, a digital circuit structure at RT level designed using any DfT technique is assumed. The proposed method enables to create a Finite State Machine with output, which can control all enable, address and clock inputs of circuit elements during the test application process. It is assumed that test patterns are inserted to circuit primary input ports and transferred through the circuit structure to selected points inside the circuit, to which they must be applied. Responses to these test patterns must then be transferred outside of the circuit and analyzed. Transfers of such diagnostic data are controlled by the test controller. Formal tools and approaches are used. The main advantage of formally described methods is that all processes are easily provable and no large evaluation of proposed methods on benchmark circuits is necessary.

show abstract

Nested Loops Degree Impact on RTL Digital Circuit Testability 1

Strnadel

2003

IFAC Proceedings Volumes

View full text Add to dashboard Cite

Testability improvements based on the combination of analytical and evolutionary approaches at RT level

Cited by 5 publications

References 13 publications

Testable design verification using Petri nets

Testable design verification using Petri nets

Formal approach to synthesis of a test controller

Nested Loops Degree Impact on RTL Digital Circuit Testability 1

Contact Info

Product

Resources

About