Lowering power consumption and increasing noise margin have become two central topics in every state of the art SRAM design. Due to parameter fluctuations in scaled technologies, stable operation is critical to obtain high yield low-voltage, low-power SRAM. Recent published works in literature have shown that the conventional 6T SRAM suffers a severe stability degradation due to access disturbances at low-power mode. Thus, several 8T and 10T cell designs have been reported, improving the cell stability. However, they either employ single-ended read port or require too large area. In this paper, we use a fully differential 8T SRAM that allows efficient bit-interleaving to achieve soft-error tolerance with conventional Error Correcting Code (ECC). It also consumes less power when compared to the conventional 6T design. A column-based dynamic supply voltage scheme is utilized to improve both the read noise margin and the write-ability. To verify the technique, a 128 64-bit of the proposed SRAM has been implemented in a standard 65 nm/1 V CMOS process. Simulation results reaffirmed that the proposed design has 2 higher noise margin and consumes 54% less power when compared to the conventional 6T design.Index Terms-Low power SRAM, low voltage SRAM, multiple port SRAM, static-noise-margin-free.

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A novel non-iterative circuit for computing division based on logarithm is proposed in the paper. Mitchell-based methods are used for the logarithmic and antilogarithmic conversions. Merging the conversion stages in the implementation is not possible if the existing antilogarithmic conversion algorithms are used. Thus, the critical path has at least two carry propagate adders (CPAs). This work introduces a new antilogarithmic algorithm to merge the two conversion stages into a single one to remove one of the two CPAs. Compared to the best existing Mitchell-based logarithmic division computation method used in a 3-D graphic system, the proposed design achieves improvements by 45.4% and 34.8%, respectively, in computation speed and area-delay product with an area overhead of 19.5%.I.

A novel non-iterative circuit for computing integer square root based on logarithm is proposed in the paper. Mitchell's methods are used for the logarithmic and antilogarithmic conversions. The proposed method merges two conversion stages into a single one to achieve better accuracy with a compact architecture. Hence, the circuit size and latency are reduced. Compared to an existing design based on the modified Dijkstra algorithm used in a coherent receiver, the proposed design is either 8 times smaller or 9 times faster for 16bit integer input.