An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS

Do, Anh-Tuan; Low, Jeremy Yung Shern; Low, Joshua Yung Lih; Kong, Zhi Hui; Tan, Xiaoliang; Yeo, Kiat Seng

doi:10.1109/tcsi.2010.2103154

Cited by 86 publications

(44 citation statements)

References 20 publications

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“…So we cannot recommend this method in practical because increasing cell ratio results larger area and the power consumption also gets increased. SRAM cells must be designed properly; otherwise it may change its state during read and write operation [10].…”

Section: Problem With Conventional 6t Sram Cellmentioning

confidence: 99%

Power and Area Efficient 10t Sram With Improved Read Stability

Geethumol¹,

S²,

Dhanusha³

2017

IJME

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In this paper, a 10T Static Random Access Memory bit cell is proposed to meet design specification for performance, stability, area and power consumption. In every state of SRAM cell designs low power and increased noise margin plays an important role. The conventional 6T SRAM cell is very much prone to noise during read operation. In order to overcome the Read SNM problem in the 6T SRAM cell designers have implemented many other SRAM configurations such as 8T, 9T, 10T. These SRAM cell configurations improve the read stability but increase the power consumption. We proposed a 10T SRAM cell which can solve all these problems by introducing the transmission gate and using stacking effect in the configuration. In this paper different SRAM cells analyzed on the basis of power and read stability and we proposed a 1-bit SRAM memory array using the proposed 10T SRAM bit cell that achieves cell stability, lower power consumption and lesser area. The proposed circuit was implemented in Mentor Graphics Design Architect, simulated using Mentor Graphics ELDO at supply voltage of 1.8V with the help of TSMC 180nm technology. Micro wind is used to draw layout of SRAM cells and peripherals.

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Section: Problem With Conventional 6t Sram Cellmentioning

confidence: 99%

Power and Area Efficient 10t Sram With Improved Read Stability

Geethumol¹,

S²,

Dhanusha³

2017

IJME

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“…One of the major advantages of transmission gate is that it eliminates the requirement of sense amplifier and precharge circuit as used in conventional 8T SRAM cell for the read purpose thus lowering the power ICAET 2016 -consumption of the cell [10]. Figure 1 shows the schematic of 8T SRAM cell.…”

Section: Read and Write Operation Of Circuitmentioning

confidence: 99%

Design and analysis of single- ended robust low power 8T SRAM cell

Gupta

Pahuja

2016

MATEC Web of Conferences

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Abstract.This paper is based on the observation of 8T single ended static random access memory (SRAM) and two techniques for reducing the sub threshold leakage current, power consumption are examined. In the first technique, effective supply voltage and ground node voltages are changed using a dynamic variable voltage level technique(VVL). In the second technique power supply is scaled down. This 8T SRAM cell uses one word line, two bitlinesand a transmission gate. Simulations and analytical results show that when the two techniques combine the new SRAM cell has correct read and write operation and also the cell contains 55.6% less leakage and the dynamic power is 98.8% less than the 8T single ended SRAM cell. Simulations are performed using cadence virtuoso tool at 45nm technology.

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“…A hefty amount of current is saved because only one logic word is activated, which is different from the existing designs where all cells in the accessed row operate simultaneously. Compared with the previous bit-interleaving schemes in [9,10], the advantage of this method is that it has less restriction to the cell topology because half-selected disturbance is removed by developing LWD instead of designing a new cell. Bit-interleaving scheme in this work is not only applicable for the 8T cell but also feasible for the subthreshold 9T cell [4] and 10T cell [5].…”

Section: Bit-interleaving Structure For U-vds Srammentioning

confidence: 99%

“…However, subthreshold cells designed in [3,4,5] suffer from the half-selected problem if bit-interleaving is used. To implement bit-interleaving, a fully differential 10T cell is proposed in [9] at the expense of area overhead and a differential 8T cell is designed in [10] by adopting a columnbased dynamic cell-supply.…”

Section: Introductionmentioning

confidence: 99%

“…Another issue is that the aforementioned SRAMs [3,4,5,9,10] could not operate efficiently at higher voltages since they were all targeted for the subthreshold operation. Actually, the characteristics of MOSFETs in the subthreshold region are significantly different from those in the super-threshold region, which brings challenges for the U-DVS SRAM design.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A 0.2 V–1.8 V 8T SRAM with Bit-interleaving Capability

Zhao

Fan

Chen

et al. 2014

IEICE Electron. Express

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An 8T SRAM with bit-interleaving capability is designed for ultra-dynamic voltage scaling applications. An adaptive body-biasing scheme is designed to improve the stability of 8T cell, which achieves 1.5 times higher noise margin compared to the non-bodybiased 8T cell. Also, a write driver is presented to enable the bitinterleaving structure, thus achieving high soft-error tolerance. A prototype 1-kb SRAM is fabricated in a standard 0.18 µm CMOS process. The measurement results show that the proposed design fulfils the functionality under supply voltage from 1.8 V to 0.3 V (0.2 V when the write wordline is boosted to 0.36 V) and the total power is reduced by four times of magnitude.

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An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS

Cited by 86 publications

References 20 publications

Power and Area Efficient 10t Sram With Improved Read Stability

Power and Area Efficient 10t Sram With Improved Read Stability

Design and analysis of single- ended robust low power 8T SRAM cell

A 0.2 V–1.8 V 8T SRAM with Bit-interleaving Capability

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