2014
DOI: 10.1587/elex.11.20140229
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A 0.2 V–1.8 V 8T SRAM with Bit-interleaving Capability

Abstract: An 8T SRAM with bit-interleaving capability is designed for ultra-dynamic voltage scaling applications. An adaptive body-biasing scheme is designed to improve the stability of 8T cell, which achieves 1.5 times higher noise margin compared to the non-bodybiased 8T cell. Also, a write driver is presented to enable the bitinterleaving structure, thus achieving high soft-error tolerance. A prototype 1-kb SRAM is fabricated in a standard 0.18 µm CMOS process. The measurement results show that the proposed design fu… Show more

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Cited by 3 publications
(3 citation statements)
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“…Table 3 summarizes the performance of the proposed pre-interleaver and compares it with interleaving circuits published in recent years. This work and Reference [27] adopted a D-flip-flop-based register to realize the memory array, while References [28][29][30] employed SRAM with fewer MOS transistors. Since the influence of peripheral auxiliary circuits, such as sense amplifiers and decoders, on the operation frequency has been eliminated, this work can achieve the highest frequency.…”
Section: Discussionmentioning
confidence: 99%
See 1 more Smart Citation
“…Table 3 summarizes the performance of the proposed pre-interleaver and compares it with interleaving circuits published in recent years. This work and Reference [27] adopted a D-flip-flop-based register to realize the memory array, while References [28][29][30] employed SRAM with fewer MOS transistors. Since the influence of peripheral auxiliary circuits, such as sense amplifiers and decoders, on the operation frequency has been eliminated, this work can achieve the highest frequency.…”
Section: Discussionmentioning
confidence: 99%
“…Moreover, the memory size in this work is larger than that in Reference [27], and less than that in References [29,30], with a higher interleaving degree and less power consumption. In Reference [28], due to the adopted process and voltage supply, the leakage current in SRAM is larger, resulting in higher power consumption than in References [29,30]. a .…”
Section: Discussionmentioning
confidence: 99%
“…Near and sub-threshold SRAM is effective to reduce power dissipation, so they are extensively used in low power applications [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]. 8T SRAM cell has taken the place of 6T cell to be a popular choice for the near and sub-threshold operation [2,3,4,5,6,7]. Unfortunately, 8T cell has additional leakage path compared to 6T cell, thus increasing the cell leakage [8].…”
Section: Introductionmentioning
confidence: 99%