Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier

Wen, Liang; Cheng, Xu; Zhou, Keji; Tian, Shudong; Zeng, Xiaoyang

doi:10.1109/tcsii.2016.2530881

Cited by 29 publications

(24 citation statements)

References 10 publications

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“…GL GR 4) Half-select issue: The half-select issue is defined as the flip of the stored value at half selected cell(row, column) during the write-back operation of IMC [12]. The C6T SRAM suffers from bit line disturbance in the row-half-selected bit cells [18]. As write word-line simultaneously enable all bitcells, including words in non-selected columns, half-selected disturbance happens in the row-half selected cells, but column-half-selected bit cells escape from half-select issue due to inactive WWLs.…”

Section: Rwl[2]mentioning

confidence: 99%

“…The dual-port 8T SRAM has been proposed for current-based compute-in-memory dot product operations [16]. However, the 8T SRAM [11], [13], [15], [16] still suffers from low array efficiency and halfselect issue [12] due to 6T-like write operations [17], [18]. The 10T SRAM reported in [19], [20] are free from computefailure and compute-disturb and compute all logic operations in a single cycle.…”

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confidence: 99%

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Local Bit-Line Sharing Robust Dual-Port 8T SRAM With Virtual VSS for Energy-Efficient In-Memory Computing Architecture

Rajput¹,

Pattanaik²,

Kaushal³

2021

Preprint

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The In-Memory Computing (IMC) architecture based on 6T, 8T, 10T SRAM fails under process-variation and suffers from compute-disturb, compute-failure, half-select issue, respectively, which affect the reliability of IMC operation. To overcome these problems, local bit-line sharing Dual-Port 8T (SDP8T) SRAM with Virtual VSS is proposed to improve the stability and energy efficiency of IMC architecture. The decouple read-write path with high-Vth transistor is used to improve the read-margin by 2.11× and reduce the read-energy by 36.35% as compared to Transpose-8T SRAM. The virtual VSS write assist is used in SDP8T SRAM to improve the write-margin by 26.49%, and lower the leakage power by 47.95% as compared to Transpose-8T SRAM. Furthermore, IMC architecture is proposed using SDP8T SRAM. In addition to the SRAM function, SDP8T-IMC architecture performs In-memory Boolean computation(IMBC) operations without compute-disturbance and compute-failure. The remarkable feature of SDP8T-IMC architecture is that it performs IMBC operation on four operands simultaneously using all four bit-line ports in a single cycle, thus doubling the throughput and obtain 11.04 fJ/bit average energy consumption at 1 V supply. The maximum operating frequency of the proposed IMC architecture is 1050 MHz at 1 V. Cumulatively, the proposed SDP8T-IMC architecture has 32.22%, 27.03%, 60.10%, 50.93%, 60.48%, 35.05%, and 65.28% reduction in energy consumption as compared to C6T, 6TCSRAM, 8+T, 8T, 10T, 12T, and 4+2T SRAM based IMC architectures, respectively. Moreover, the proposed IMC architecture is configured as Binary Content Addressable Memory (BCAM) for searching applications which achieves 0.60fJ energy consumption per search/bit at 1 V.

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Section: Rwl[2]mentioning

confidence: 99%

mentioning

confidence: 99%

Local Bit-Line Sharing Robust Dual-Port 8T SRAM With Virtual VSS for Energy-Efficient In-Memory Computing Architecture

Rajput¹,

Pattanaik²,

Kaushal³

2021

Preprint

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“…The bit-interleaving-enabled 8T SRAM architecture is proposed by Wen et al [106]. The proposed cell features shared data-aware write structure and utterly eliminates the half-select disturbance.…”

Section: Data-aware Power-efficient Sram Cellmentioning

confidence: 99%

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

Singh¹

2017

Field - Programmable Gate Array

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The design of low-power SRAM cell becomes a necessity in today's FPGAs, because SRAM is a critical component in FPGA design and consumes a large fraction of the total power. The present chapter provides an overview of various factors responsible for power consumption in FPGA and discusses the design techniques of low-power SRAMbased FPGA at system level, device level, and architecture levels. Finally, the chapter proposes a data-aware dynamic SRAM cell to control the power consumption in the cell. Stack effect has been adopted in the design to reduce the leakage current. The various peripheral circuits like address decoder circuit, write/read enable circuits, and sense amplifier have been modified to implement a power-efficient SRAM-based FPGA.

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“…It is particularly eligible for power-efficient applications where the power consumption is highly constrained while the performance requirement is secondary. Accordingly, many power-hungry digital systems [5][6][7][8][9] and low-power memories [10][11][12][13][14] benefit tremendously from sub-threshold circuits.…”

Section: Introductionmentioning

confidence: 99%

65 nm sub‐threshold logic standard cell library using quasi‐Schmitt‐trigger design scheme and inverse narrow width effect aware sizing

Wen¹,

Liu²,

Zhang³

et al. 2020

IET Circuits, Devices & Systems

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In this study, the authors propose a sub-threshold standard cell library in which the quintessence is a quasi-Schmitttrigger logic design scheme and the inverse narrow width effect aware sizing method. The techniques can improve the I onto -I off ratio of the logic cells effectively and provide a significant suppression in leakage current, enhancing the robustness of the circuits. Simulation results show that the NAND3 and NOR3 logics with the new techniques achieve 40-60% and 30-50% reductions in leakage power compared with conventional logic circuits, respectively, when the voltage is scaled down to subthreshold region. Again, they also exhibit considerable improvements in process variation immunity and power-delay product.

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Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier

Cited by 29 publications

References 10 publications

Local Bit-Line Sharing Robust Dual-Port 8T SRAM With Virtual VSS for Energy-Efficient In-Memory Computing Architecture

Local Bit-Line Sharing Robust Dual-Port 8T SRAM With Virtual VSS for Energy-Efficient In-Memory Computing Architecture

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

65 nm sub‐threshold logic standard cell library using quasi‐Schmitt‐trigger design scheme and inverse narrow width effect aware sizing

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