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An 8T SRAM with bit-interleaving capability is designed for ultra-dynamic voltage scaling applications. An adaptive body-biasing scheme is designed to improve the stability of 8T cell, which achieves 1.5 times higher noise margin compared to the non-bodybiased 8T cell. Also, a write driver is presented to enable the bitinterleaving structure, thus achieving high soft-error tolerance. A prototype 1-kb SRAM is fabricated in a standard 0.18 µm CMOS process. The measurement results show that the proposed design fulfils the functionality under supply voltage from 1.8 V to 0.3 V (0.2 V when the write wordline is boosted to 0.36 V) and the total power is reduced by four times of magnitude.

In this paper, a 3-5GHz IR-UWB transmitter based on 0.18µm CMOS is presented. The transmitter has the features of low power and low complexity by using a symmetrical "Ping-Pong" structure. Two digital transmitters are combined to overcome the noise due to effect of charge injection. A synchronized pulse position modulation and demodulation method is proposed. It improves the efficiency of the transmitter while keeping the receiver simplified. A template-based digital delay generation scheme is used to improve the delay accuracy. Measurement results show that no unwanted spur is generated. The transmitter consumes 36 pJ/b to achieve a maximum data rate of 200 Mb/s.

To further expand the output voltage range of the converter, a current-starved voltage controlled delay line is proposed in the controller of DC-DC converter to obtain an ultra low voltage of 0.5 V. When the input voltage is 3.3 V, the output voltage of the converter can be dynamically regulated from 0.5 to 2.0 V. The output voltage tracking speed is less than 7.5 ls/V and the recovery speed is 33 ls/A for a load current step from 0.6 to 0.2 A at output voltage of 0.5 V. The chip area is 1.75 mm 9 1.33 mm in a 0.18 lm standard CMOS process.