We present a high performance implementation of a belief propagation decoder for decoding low-density parity-check (LDPC) codes on a fixed point digital signal processor. A simplified decoding algorithm was used and a stopping criteria for the iterative decoder was implemented to reduce the average number of required iterations. This leads to an implementation with increased throughput compared to other implementations of LDPC codes or Turbo codes. This decoder is able to decode at 5.4Mbps on a Texas Instruments TMS320C64xx DSP running at 600MHz.

Abstract-The degree distribution of low-density parity-check (LDPC) codes is optimized for systems that iterate over the receiver frontend, e.g., soft detector, demodulator, equalizer, etc., and the LDPC decoder. The overall extrinsic information transfer (EXIT) function of an iterative LDPC decoder is computed, based on the code's own EXIT chart, under the Gaussian assumption. While the optimization of the variable node distribution is a nonlinear problem, the optimization of the check node distribution is shown to be a linear problem. This fact is exploited to design codes where both the variable and the check node distributions are optimized, resulting in more robust constructions. The technique presented requires only knowledge of the measured EXIT function of the receiver frontend.

Three areas of ongoing research in channel coding are surveyed, and recent developments are presented in each area: spatially coupled Low-Density Parity-Check (LDPC) codes, nonbinary LDPC codes, and polar coding.

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