We present an area-efficient parallel architecture that implements the constant-geometry, in-place Fast Fourier Transform. It consists of a specific-purpose processor array interconnected by means of a perfect unshuffle network. For a radix r transform of N = r n data of size D and a column of P = r p processors, each processor has only one local memory of N=rP words of size rD, with only one read port and one write port that, nevertheless, make it possible to read the r inputs of a butterfly and write r intermediate results in each memory cycle. The address generating circuit that permits the in-place implementation is simple and the same for all the local memories. The data flow has been designed to efficiently exploit the pipelining of the processing section with no cycle loss. This architecture reduces the area by almost 50% of other designs with a similar performance.

One of the main disadvantages of using D-type double-edge triggered flip-flops (DET-FF's) in VLSI systems design is the number of transistors required. In this paper two new DET-FF circuits (one static, the other dynamic) are proposed in which the number of transistors is reduced to a number similar to that for classic single-edge triggered flip-flops (SET-FF's). Both new circuits not only behave correctly when operated at high frequency but also offer a good level of immunity to metastability problems (static) and race problems (dynamic), as well as presenting a simple straightforward layout. These considerations offer wider practical and economic applications for the use of DET-FF's in VLSI systems design.

The compensation of scale factor imposes signifcant computation overhead on the CORDIC algorithm. In this paper we will propose two algorithms and architectures in order to perform the compensation of the scale factor in parallel with the computation of the CORDIC iterations. This way it is not necessary to carly out the final multiplication or add scaling iterations in order to achieve the compensation. With the architectures we propose the dependence on n of the compensation of the scale factor disappears, and this considerably reduces the latency of the system. The architectures developed are optimized solutions for the different operating modes of the CORDIC both in conventional and in redundant arithmetic. 0 (rotation mode) or it is taken to the coordinate axis (vectoring mode). The algorithm is based on the decomposition of the rotation angle into known elementary angles. The basic iteration or microrotation is: By means of the CORDIC algorithm, a vector of coordinates (x,y) is rotated an angle * This work was supported by the Ministq of Education and Science (CICYT) of Spain under project TIC-92-0942 258 1063-6862195 $4.00 0 1995 IEEE Session 8: Arithmetic I1x(i+l)=x(i) + o,2'y(i) y(i+l)=y(i)o,2'x(i) z(i+l)=z(i)o,tg-'2-'

No abstract

No abstract