Area-efficient architecture for Fast Fourier transform

Hidalgo, Juan Antonio Auñón; López, Juan José Vaquero; Argüello, Francisco; Zapata, Emilio L.

doi:10.1109/82.752951

Cited by 33 publications

(21 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…An area-efficient memory scheme has been proposed in [7] to eliminate the spatial-conflict bottleneck without using multi-banked memory for achieving both performance and area advantages. Since the merged-banked memory contains only one address decoder within the memory module, exactly one address generation unit (AGU) is needed for accessing the memory.…”

Section: B Pseudo-banked Memorymentioning

confidence: 99%

See 1 more Smart Citation

Efficient memory management for FFT processors

Luo

Shieh

Liu

et al. 2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

View full text Add to dashboard Cite

This paper presents an efficient memory management scheme for memory-based architecture of Fast Fourier Transform (FFT). A new data relocating scheme is proposed to merge multiple banks for alleviating the area requirement as well as the power dissipation of memory-based FFT. The proposed memory addressing method can effectively deal with merged-banked single-ported memory with high-radix processing elements. Compared to conventional memory-based FFT designs using two-ported memories, the derived architecture reveals better performance in area requirement and power consumption.

show abstract

Section: B Pseudo-banked Memorymentioning

confidence: 99%

“…al. [7] proposed a merged-banked memory structure that stores r required butterfly data in the same memory entry without requiring multi-banked memory to effectively reduce the area of memory.…”

Section: Introductionmentioning

confidence: 99%

Efficient memory management for FFT processors

Luo

Shieh

Liu

et al. 2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

View full text Add to dashboard Cite

show abstract

“…1. If large amount of data must be stored, e.g., in long FFTs, memorybased structures [1][2][3] are attractive. For relatively small storage requirements, however, register-based structures are better alternatives, and thus, they are considered in this paper.…”

Section: Introductionmentioning

confidence: 99%

Stride Permutation Networks for Array Processors

Jarvinen

Salmela

Sorokin

et al. 2007

J VLSI Sign Process Syst Sign Im

View full text Add to dashboard Cite

In several digital signal processing algorithms, computational nodes are organized in consecutive stages and data is reordered between these stages. Parallel computation of such algorithms with reduced number of processing elements implies that several computational nodes are assigned to each element. As a drawback, permutations become more complex and require data storage. In this paper, a systematic design methodology for stride permutation networks is derived. These permutations are represented with Boolean matrices, which are decomposed and mapped directly onto register-based networks. The resulting networks are regular and scalable and they support any stride of power-of-two. In addition, the networks reach the lower bound in the number of registers indicating area-efficiency. Since the proposed methodology is systematic, it can be exploited in automated design generation.

show abstract

“…An ASSP can compromise advantages of custom ASIC chips and general DSP chips [3][4][5][6][7][8]. In other words, an ASSP can adopt high performance and low power of ASIC chips and flexibility of DSP chips.…”

Section: Introductionmentioning

confidence: 99%

SPOCS: Application Specific Signal Processor for OFDM Communication Systems

Baek

Kim

Sunwoo

2008

J Sign Process Syst Sign Image Video Technol

View full text Add to dashboard Cite

This paper presents an Application-Specific Signal Processor (ASSP) for Orthogonal Frequency Division Multiplexing (OFDM) Communication Systems, called SPOCS. The instruction set and its architecture are specially designed for OFDM systems, such as Fast Fourier Transform (FFT), scrambling/descrambling, puncturing, convolutional encoding, interleaving/deinterleaving, etc. SPOCS employs the optimized Data Processing Unit (DPU) to support the proposed instructions and the FFT Address Generation Unit (FAGU) to automatically calculate input/output data addresses. In addition, the proposed Bit Manipulation Unit (BMU) supports efficient bit manipulation operations. SPOCS has been synthesized using the SEC 0.18 μm standard cell library and has a much smaller area than commercial DSP chips. SPOCS can reduce the number of clock cycles over 8% 53% for FFT and about 48%~84% for scrambling, convolutional encoding and interleaving compared with existing DSP chips. SPOCS can support various OFDM communication standards, such as Wireless Local Area Network (WLAN), Digital Audio Broadcasting (DAB), Digital Video Broadcasting-Terrestrial (DVB-T), etc.

show abstract

Area-efficient architecture for Fast Fourier transform

Cited by 33 publications

References 11 publications

Efficient memory management for FFT processors

Efficient memory management for FFT processors

Stride Permutation Networks for Array Processors

SPOCS: Application Specific Signal Processor for OFDM Communication Systems

Contact Info

Product

Resources

About