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In this work, we present a normally-off recessed-gate AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) using a TiO2/SiN dual gate-insulator. We analyzed the electrical characteristics of the proposed device and found that the dual gate-insulator device achieves higher on-state currents than the device using a SiN gate-insulator because the high-k insulator layer of the dual gate-insulator improves the gate-controllability. The device using a TiO2/SiN gate-insulator shows better gate leakage current characteristics than the device with only TiO2 gate-insulator because of the high quality SiN gate-insulator. Therefore, the device using a dual gate-insulator can overcome disadvantages of a device using only TiO2 gate-insulator. To better predict the power consumption and the switching speed, we simulated the specific on-resistance (Ron, sp) according to the gate-to-drain distance (LGD) using the two-dimensional ATLAS simulator. The proposed device exhibits a threshold voltage of 2.3 V, a maximum drain current of 556 mA/mm, a low Ron, sp of 1.45 mΩ·cm2, and a breakdown voltage of 631 V at an off-state current of 1 μA/mm with VGS = 0 V. We have confirmed that a normally-off recessed-gate AlGaN/GaN MIS-HEMT using a TiO2/SiN dual gate-insulator is a promising candidate for power electronic applications.

In this work, a polycrystalline silicon (poly-Si) double-gate metal-oxide-semiconductor field-effect transistor-based stacked multi-layer (ML) onetransistor dynamic random-access memory for the embedded memory is proposed using technology computer-aided simulation. Although poly-Si has advantages of low-cost fabrication and implementation of three-dimensional structure, poly-Si devices suffer from low on-state current (I on ) due to the low mobility and the scattering by the grain boundary (GB) trap. The stacked ML structure is proposed to improve low I on . As a result of simulation, the ML device obtained a high I on of 87.92 μA μm −1 . Owing to the enhancement of I on , the ML achieved a high SM of 30.44 μA μm −1 . A retention time (RT) of the proposed ML device in the simulation exhibited 2.94 ms even at a high temperature of 358 K. Moreover, the proposed ML device demonstrates superior reliability in terms of memory operations (RT >100 μs) for randomly distributed GBs.

In this paper, a 1T-DRAM based on the junctionless field-effect transistor (JLFET) with an ultrathin polycrystalline silicon layer was designed and investigated by using technology computer-aided design simulation (TCAD). The application of a negative voltage at the control gate results in the generation of holes in the storage region by the band-to-band tunneling (BTBT) effect. Memory characteristics such as sensing margin and retention time are affected by the doping concentration of the storage region, bias condition of the program, and length of the intrinsic region. In addition, the gate acts as a switch that controls the transfer characteristics while the control gate plays a role in retaining holes in the hold state. The device was optimized, considering various parameters such as the doping concentration of the storage region (Nstorage), intrinsic region length (Lint), and operation bias conditions to obtain a high sensing margin of 49.7 μA/μm and a long retention time of 2 s even at a high temperature of 358 K. The obtained retention time is almost 30 times longer than that predicted for modern DRAM cells by the International technology roadmap for semiconductors (ITRS).

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