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This paper presents a novel highly efficient 5-stage RF rectifier in SMIC 65 nm standard CMOS process. To improve power conversion efficiency (PCE) and reduce the minimum input voltage, a hybrid threshold self-compensation approach is applied in this proposed RF rectifier, which combines the gate-bias threshold compensation with the body-effect compensation. The proposed circuit uses PMOSFET in all the stages except for the first stage to allow individual body-bias, which eliminates the need for triple-well technology. The presented RF rectifier exhibits a simulated maximum PCE of 30% at −16.7 dBm (20.25 µW) and produces 1.74 V across 0.5 MΩ load resistance. In the circumstances of 1 MΩ load resistance, it outputs 1.5 V DC voltage from a remarkably low input power level of −20.4 dBm (9 µW) RF input power with PCE of about 25%.