In this paper, we propose a novel reconfigurable processor using dynamically partitioned single‐instruction multiple‐data (DP‐SIMD) which is able to process multimedia data. The SIMD processor and parallel SIMD (P‐SIMD) processor, which is composed of a number of SIMD processors, are usually used these days. But these processors are inefficient because all processing units (PUs) should process the same operations all the time. Moreover, the PUs can process different operations only when every SIMD group operation is predefined. We propose a processor control method which can partition parallel processors into multiple SIMD‐based processors dynamically to enhance efficiency. For performance evaluation of the proposed method, we carried out the inverse transform, inverse quantization, and motion compensation operations of H.264 using processors based on SIMD, P‐SIMD, and DP‐SIMD. Experimental results show that the DP‐SIMD control method is more efficient than SIMD and P‐SIMD control methods by about 15% and 14%, respectively.

In this paper, we propose an efficient architecture for a real‐time image stitching engine for vision SoCs found in motor vehicles. To enlarge the obstacle‐detection distance and area for safety, we adopt panoramic images from multiple telegraphic cameras. We propose a stitching method based on a fixed homography that is educed from the initial frame of a video sequence and is used to warp all input images without regeneration. Because the fixed homography is generated only once at the initial state, we can calculate it using SW to reduce HW costs. The proposed warping HW engine is based on a linear transform of the pixel positions of warped images and can reduce the computational complexity by 90% or more as compared to a conventional method. A dual‐core SW/HW image stitching engine is applied to stitching input frames in parallel to improve the performance by 70% or more as compared to a single‐core engine operation. In addition, a dual‐core structure is used to detect a failure in state machines using rock‐step logic to satisfy the ISO26262 standard. The dual‐core SW/HW image stitching engine is fabricated in SoC with 254,968 gate counts using Global Foundry's 65 nm CMOS process. The single‐core engine can make panoramic images from three YCbCr 4:2:0 formatted VGA images at 44 frames per second and frequency of 200 MHz without an LCD display.

In this letter, we propose a new compression method for a high dimensional support vector machine (SVM). We used singular value decomposition (SVD) to compress the norm part of a radial basis function SVM. By deleting the least significant vectors that are extracted from the decomposition, we can compress each vector with minimized energy loss. We select the compressed vector dimension according to the predefined threshold which can limit the energy loss to design criteria. We verified the proposed vector compressed SVM (VCSVM) for conventional datasets. Experimental results show that VCSVM can reduce computational complexity and memory by more than 40% without reduction in accuracy when classifying a 20,958 dimension dataset.

In this paper, we proposed a advanced hardware engine architecture for high speed and high detection rate image recognitions. We adopted the HOG-LBP feature extraction algorithm and more parallelized architecture in order to achieve higher detection rate and high throughput. As a simulation result, the designed engine which can search about 90 frames per second detects 97.7% of pedestrians when false positive per window is 10-4 .

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