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For the first time, we have integrated poly-Si gate CMOS-FETs with Hf02-A1,O1 laminate gate dielectric (EOT=14.6A) grown by Atomic Layer Deposition (ALD). The gate leakage currents are 3.7pA/cm2 (Vg=+l.OV) for nMOSFET and 0.2 pA/cm' (Vg=-I .OV) for pMOSFET. These extremely low leakage currents sufficiently satisfy the specification (EOT= 12-20A, Jg=2.2mA/cm2) estimated by ITRS. The fixed charge is decreased using Hf02-A1,0, laminate gate dielectric, and consequently flatband voltage ( V ' ) shift is within 0.20V compared with the Vjb of nitrided SiO, control. In addition, the low gate induced drain leakage (GIDL) is obtained using HfO,-A1,O1 laminate gate dielectric. Ion vs. Ioff plots of the planar CMOS transistor with high-k is shown for the first time in this paper. The measured saturation currents at 1.2V Vdd are 430pA/pm (I,rr=lOnA/pm) for nMOSFET and 160pA/ um (IoR=IOnA/um) for pMOSFET. These are the highest currents compared with previous reports for the planar poly-Si gate CMOSFETs with high-k gate dielectric.