Recent lightweight block cipher competition (FELICS Triathlon) evaluates efficient implementations of block ciphers for Internet of things (IoT) environment. In the competition, the implementation of HIGHT block cipher achieved the most efficient lightweight block cipher, in terms of code size (ROM), memory (RAM), and execution time. In this paper, we further investigate lightweight features of HIGHT block cipher and present the optimized implementations of both software and hardware for low-end IoT platforms, including resource-constrained devices (8-bit AVR and 32-bit ARM Cortex-M3) and application-specific integrated circuit (ASIC). By using proposed optimization methods, the implemented HIGHT block cipher shows better performance compared to previous state-of-the-art implementations.

No abstract

Implementing countermeasure against power analysis-based attack is a critical issue in cryptographic hardware implementation. Protection schemes such as masking or Threshold Implementation (TI) have been proposed for hardware protection, but they have shortages like insufficient protection ability, or excessive hardware overhead. In this paper, we present low cost hetero S-box hardware implementation, where S-box groups for ARIA algorithm can be implemented using the coefficients with different hardware cost. Additional area reduction scheme using isomorphism sharing between S-boxes are also proposed. The proposed heterogeneous ARIS S-box has been implemented using 28nm CMOS process, and it showed 39% area saving with 30% of power saving. The proposed hardware also passed the security test, showing that it is verified as secure against power analysisbased attacks.

No abstract

No abstract