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High NA immersion and EUV lithography processes are challenged to meet stringent control requirements for the 22 nm node and beyond. Lithography processes must balance resolution, LWR and sensitivity (RLS) performance tradeoffs while scaling resist thickness to 100 nm and below 1-3 . Hardware modules including coat, bake and development seek to enable resist processes to balance RLS limitations. The focus of this paper is to study the fundamentals of the RLS performance tradeoffs through a combination of calibrated resist simulations and experiments.This work seeks to extend the RLS learning through the creation of calibrated resist models that capture the exposure kinetics, acid diffusion properties, deprotection kinetics and dissolution response as a function of PAG loading in a 193 nm polymer system. The calibrated resist models are used to quantify the resolution and sensitivity performance tradeoffs as well as the degradation of resist contrast relative to image contrast at small dimensions.Calibrated resist simulations are capable of quantifying resolution and sensitivity tradeoffs, but lack the ability to model LWR. LWR is challenging to simulate (lattice models) and to measure; due to the dependence on spectral frequency. This paper seeks to use micro-bridging experiments as means to better understand the statistical nature of LWR. Microbridging analysis produces a statistical distribution of "discrete bridging events" that encompasses practical variations across scanner, track and resist. Micro-bridging and LWR experiments are done using a 1.2 NA immersion system on 45 nm space structures (90 nm pitch) as a means to demonstrate the concept, but the methodology can also be used to study EUVL processes as the technology matures. The understanding of the RLS performance tradeoffs enables TEL to develop future hardware and processes that support industry scaling goals.

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As Extreme ultraviolet (EUV) lithography technology shows promising results below 40nm feature sizes, TOKYO ELECTRON LTD.(TEL) is committed to understanding the fundamentals needed to improve our technology, thereby enabling customers to meet roadmap expectations. TEL continues collaboration with imec for evaluation of Coater/Developer processing sensitivities using the ASML Alpha Demo Tool for EUV exposures. The results from the collaboration help develop the necessary hardware for EUV Coater/Developer processing. In previous work 1 , processing sensitivities of the resist materials were investigated to determine the impact on critical dimension (CD) uniformity and defectivity. In this work, new promising resist materials have been studied and more information pertaining to EUV exposures was obtained. Specifically, post exposure bake (PEB) impact to CD is studied in addition to dissolution characteristics and resist material hydrophobicity. Additionally, initial results show the current status of CDU and defectivity with the ADT/CLEAN TRACK ACT™12 lithocluster. Analysis of a five wafer batch of CDU wafers shows within wafer and wafer to wafer contribution from track processing. A pareto of a patterned wafer defectivity test gives initial insight into the process defects with the current processing conditions. From analysis of these data, it's shown that while improvements in processing are certainly possible, the initial results indicate a manufacturable process for EUV.