Gate-bias stress causes changes in the electrical stability of thin-film transistors (TFTs), and this can degrade the device performance. This research highlights the effects of environmental conditions on the electrical stability of pentacene TFTs in which cross-linked poly(4vinylphenol-co-methyl methacrylate) (PVP-co-PMMA) was utilized as a gate dielectric layer. Under negative gate-bias stress, the fabricated TFTs exposed to ambient air showed a positive threshold voltage shift, whereas the devices under vacuum exhibited a negative threshold voltage shift. Furthermore, consecutive on/off switching operation of pentacene TFTs under ambient air induced an increase in the on-state drain current. These results are explained through the interaction between water molecules and PVP-co-PMMA, which causes the accumulation of holes in the TFT channel region having higher conductance.

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We investigate the effects of environmental conditions on the electrical stability of spin-coated 5,11-bis(triethylsilylethynyl)anthradithiophene (TES-ADT) thin-film transistors (TFTs) in which crosslinked poly(4-vinylphenol-co-methyl methacrylate) (PVP-co-PMMA) was utilized as a gate insulator layer. Atomic force microscopy observations show molecular terraces with domain boundaries in the spin-coated TEST-ADT semiconductor film. The TFT performance was observed to be superior in the ambient air condition. Under negative gate-bias stress, the TES-ADT TFTs showed a positive threshold voltage shift in ambient air and a negative threshold voltage shift under vacuum. These results are explained through a chemical reaction between water molecules in air and unsubstituted hydroxyl groups in the cross-linked PVP-co-PMMA as well as a charge-trapping phenomenon at the domain boundaries in the spin-coated TES-ADT semiconductor.

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Field-effect transistors (FETs) are considered promising devices for future development owing to their application in large-area electronics. In this research, we focus on the fabrication and optimization of the ferroelectric phase of an FET by utilizing poly(vinylidene fluoride co-hexafluoropropylene) [P(VDF-co-HFP)] as a gate insulator and pentacene as an organic semiconductor under different annealing conditions. The FET was fabricated by mixing P(VDF-co-HFP) with a preformulated concentration of methyl ethyl ketone and by spin coating this mixture onto the gate electrode. The obtained gate insulator was annealed for 1 h at temperatures ranging from 110 to 170 °C in increments of 20 °C for an analysis of the underlying effect of temperature on the properties of P(VDF-co-HFP). The results show that the FET fabricated at the optimized temperature of 150 °C exhibits significantly improved hysteresis loop and on/off ratio. This investigation led to the development of a simple method of designing and preparing an FET with excellent electrical characteristics.