An extended Norde plot is described which makes it possible to determine the series resistance, barrier height, and ideality factor from one I-V measurement of a Schottky barrier diode. A theoretical derivation is performed followed with experimental data, which demonstrates the feasibility of the method.

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Complementary Si MESFET's (CMES) for integrated circuits using silicon-on-sapphire are described. Not only the gates, but also the source and drain of the n-and p-transistors are Schottky junctions, using very high barrier heights for the gates and low barrier heights for source and drain. Only two Schottky metals are used: one, Ir o r Pt, giving a high barrier on nSi, and hence low on psi; the other, Er o r Tb, showing the opposite behaviour. The basic differences between MES and MOS are pointed out and design criteria for CMES inverters using normally-off type transistors are given. The feasibility of the technology is shown by an experimental inverter transfer curve, using only one bias supply, and high radiation hardness is demonstrated by measurements up to 10 Mrad. Another CMES advantage is the lower steady-state power consumption which is due to the low supply voltage, < 0.5 V. Computer simulation of a ring oscillator indicates a stage delay of 2 ns for 2-pm gate-length technology.

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