Articles you may be interested inFocused helium and neon ion beam induced etching for advanced extreme ultraviolet lithography mask repair Thermal modeling of extreme ultraviolet and step and flash imprint lithography substrates during dry etch Reactive ion etching ͑RIE͒ and inductively coupled plasma ͑ICP͒ Cr etch processes have been evaluated for fabrication of extreme ultraviolet lithography masks on 200 mm substrates. Experiments were completed to optimize the Cr etch rate, etch rate uniformity, and Cr to resist selectivity for both etch processes. The best ICP process was found to have superior etch rate, etch rate uniformity, and comparable Cr to resist selectivity to the RIE process. The effect of exposed Cr area on the Cr to resist selectivity, critical dimension ͑CD͒ bias, and CD bias 3 was also investigated. A decrease in exposed Cr area from 95% to 7% was found to dramatically increase the Cr etch rate, leading to an increase in the Cr to resist selectivity. Lower Cr loading was also found to decrease the CD bias and CD bias 3. The average CD bias was very high for both processes, with the ICP etch process having a higher CD bias ͑143 nm͒ than the RIE process ͑89 nm͒. The CD bias uniformity was significantly lower for the ICP process ͑32 nm, 3͒ when compared to the RIE process ͑71 nm, 3͒.

Initial stages of growth of silicon on dielectric surface proceeds through Volmer-Webber growth mode (through island formation) and coalescence of islands to form a continuous thin film layer. Growth of silicon nanocrystals on dielectric surface can be achieved by controlling the nucleation and growth kinetics of these nanocrystals on the dielectric surface. In this study, we present CVD growth of Si nanocrystals on oxide, oxynitride and nitride surfaces using silane based chemistry. The effect of process conditions such as deposition temperature, precursor flow rate, carrier gas on nanocrystal incubation time, size and density of nanocrystals was studied. The nucleation and growth rate of the silicon nanocrystals is also a strong function of the surface chemistry, surface structure and strain in the dielectric film. We have studied the effect of oxide deposition temperature and surface pretreatments on the nucleation and growth characteristics of the silicon nanocrystals.

The three-layer absorber stack for EUVL reticles currently consists of an absorber, repair buffer and etch stop layers. The repair buffer should exhibit high etch selectivity during the absorber etch processes (i.e. pattern transfer and focused ion beam (FIB) repair), be thermally and electrically conductive, optimally thin and have high etch selectivity to the siliconcapping layer over the Mo/Si multi-layer mirror. The absorber materials that have been studied in the past are TaSiN and Cr with SiON as the repair buffer on top of a Cr etch stop layer. The SiON repair buffer is insulating, exhibiting low thermal and electrical conductivity. Also, the required thickness for FIB repair is greater than 750 Å using a standard 30-keV Ga + FIB tool, 1 while the etch selectivity to the silicon capping layer during pattern transfer is less than five to one necessitating a Cr etch stop. A sputtered carbon repair buffer exhibiting the required qualities has been studied. The carbon film is thermally and electrically conductive and exhibits extremely high reactive ion etch selectivity to the silicon-capping layer. Carbon also has the lowest sputter yield out of all the elements opening a larger FIB repair process window without using gas-assisted etching. A conductive repair buffer also prevents the possibility of static charge buildup on the mask that could damage patterns during an electrostatic discharge.

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Gravitation toward a dry silicon etch process for electron projection lithography ͑EPL͒ mask fabrication is beneficial because of the concomitant increase in the available membrane area. In order to help understand the complex Bosch etch process and its dependence upon hardware design and process parameters for scattering with angular limitation in projection election beam lithography ͑SCALPEL͒ mask fabrication, a combined equipment and feature scale model has been employed. For case studies such as varying the deposition cycle time or ramping the bias power, computed sidewall profiles from the model deviate from experimental data by only about 5.5%. Given the extreme complexity of the Bosch process, this correlation is considered excellent. The best experimental Bosch etch conditions produce SCALPEL substrates with an effective silicon etch rate of 2.7 m/min, 6.1% etch uniformity, selectivity to tetraethyl orthosilicate Ͼ240:1, and average strut sidewall angles of 87.4°. Introduction of hardware into the chamber results in partially blocking the transport of important etch and polymer deposition species to the wafer, thereby altering the etch and passivation rates. The provided learning is applicable to projection reduction exposure with variable axis immersion lenses format EPL masks as well.