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The effect of the sidewall spacer thickness on the hot-carrier degradation of buried-channel PMOS transistors with a sidewall-offset single-drain structure was studied. At the bias stress condition of maximum gate current, a large degradation was observed for transistors with no overlap between gate and drain. Results of measurements using the charge-pumping technique suggest that trapping of a large number of electrons in the CVD SiO, sidewall spacer is responsible for the enhanced degradation. This was also confirmed by the measurement of the threshold voltage as a function of drain bias. N submicrometer CMOS, PMOS transistors with the p+ I drain displayed by a sidewall spacer and without the pregion are often used because of the simple fabrication process. Hot-carrier degradation of PMOSFET's is becoming more serious in the submicrometer regime. In this work, the effect of the sidewall spacer thickness on the hot-carrier degradation of sidewall-offset single-drain PMOS transistors was studied.The most serious hot-carrier degradation for PMOS is caused by injection of drain avalanche hot electrons into the oxide near the drain [I]. The trapping of negative charge near the drain results in a reduction in the electrical channel length of the transistor [l]. This channel shortening causes PMOSFET's to show a positive shift in threshold voltage V,, and an increase in linear region peak transconductance g , .PMOS transistors with n + polysilicon gates were fabricated. After the n-well formation and LOCOS isolation, punchthrough stopping implantation of phosphorus was performed at E = 220 keV. This was followed by an implantation of boron to a dose of 5 x 10I2/cm2 at E = 15 keV to obtain a V,, of about -0.7 V for the long channel. Then the 12-nm-thick gate oxide was grown. According to the process simulation, the net surface concentration of p-type impurities is 1.5 x 101'/cm3 and the junction depth of the counterdoping layer is about 0.12 pm. Sidewall spacers were formed by CVD SiO, deposition followed by reactive ion etching. Three thicknesses of sidewall spacers, 70, 100, and 145 nm, were Manuscript IEEE Log Number 9107727. prepared. The source and drain regions were formed by BF, implantation and annealing at 900°C for 20 min in N, .The lateral diffusion distance of the drain region from the gate edge was about 110 nm. From this, the gate-to-drain overlap distance was estimated to be 40, 10, and -35 nm for sidewall spacer thicknesses of 70, 100, and 145 nm, respectively. The diffusion distance was determined by plotting the channel resistance as a function of the gate length. It was also found that the transistors with differing sidewall spacer thicknesses have similar source/drain series resistances of about 120 ? 10 Q . Consequently, the transistors show almost identical characteristics when V,, and the saturated drain current are plotted against the effective channel length Le,.The degradation of PMOS transistors stressed at the condition of maximum gate current, which is known to give the maximum degradati...

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Ti silicide technology using an Al/Ti bilayer is investigated to reduce TiSi2 sheet resistance on the arsenic (As)-implanted Si surface. A 38% reduction resulting in the sheet resistance value of 1.62 Ω/sq was obtained using the bilayer of 5 nm Al/55 nm Ti. The resistivity of the film is 14.3 µΩ·cm. These films showed a very smooth silicide/Si interface. X-ray diffraction observation shows a C54 phase with high (010) orientation. Void formation was not detected by transmission electron microscope (TEM) and scanning electron microscope (SEM) observations.

The effect of the sidewall spacer thickness on the hot-carrier degradation of sidewall-offset single drain PMOS transistors was studied. At the stress bias condition of maximum gate current, a large degradation was observed when there is no overlap between gate and drain. The trapping of a large number of electrons in the sidewall oxide spacer is attributed to this. In the off-state, PMOS transistors were degraded by electrons generated by the band-to-band tunnelling process. Transistors with no gate-to-drain overlap show linle degradation at relatively low V,. because of the small drain leakage current by band-to-band tunnelling. However, as V, is increased and the drain leakage current reaches a certain level, the degree of degradation drastically increases. As in the case of the DC stress test at the peak gate current, this is probably a result of enhanced trapping of injected electrons in the sidewall spacer. These results suggest that there should be an overlap between gate and drain but that the overlap distance should be kept to a minimum in order to maximize t h e hotcarrier resistance of PMOSFETS. The single drain PMOS transistor with the optimum sidewall spacer thickness has a lifetime which is much longer than 10 years at an 1 operation voltage of -3.3V.