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This paper describes the design of a masterslice LSI with two‐input equivalent 6000 gates (three‐input 4000 gates). It uses 2 μm CMOS dual Al interconnect process technology and has application to medium and small computers, terminals and peripheral equipment. It is shown that a three‐input bent‐type gate basic cell effectively realizes high integration because various logic gates can be constructed with small areas. to realize high speed, the chip is designed in several blocks. the intra‐block net uses short interconnects, whereas the inter‐block net is driven by buffers with high load drive capability. Special clock supply circuits for small clock signal skew and a register‐file to accommodate a small capacity RAM into LSI are designed. the number of wiring channels is determined based on the theoretical wiring length, and it has been confirmed that channel utilization agrees with the theoretical value. Since it is important that a masterslice LSI be designed to its specifications within a short time, a method is developed to calculate accurately the circuit delay time during the design. Evaluation of the test LSIs shows that the average gate delay time of 1.81 ns is obtained; this agrees to within 5.4% of the calculated delay time.

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Right) FIGURE 1-The hierarchical structure of the chip.CMOS BUILDING block VLSIs with integration ranging from 10k to 20k gates, will be reported. Required layout design time was comparable to that of conventional gate arrays. The design used 2 p CMOS technology and an automated building block approach.