This paper presents quasi-3-D simulation results of SEE-induced charge collection in UHV/CVD SiGe HBTs. Depending on the bias and load condition, a significant fraction of electrons can be collected by the emitter rather than the collector. Most of the generated holes are collected by the substrate for deep ion strikes, and by the base for shallow ion strikes. A higher substrate doping can worsen the upset of the circuit function, despite the reduced total amount of charge collected. A lower substrate doping and a lower collector-substrate junction reverse bias are desired to improve SEU hardness.

Shift registers featuring radiation-hardening-by-design (RHBD) techniques are realized in IBM 8HP SiGe BiCMOS technology. Both circuit and device-level RHBD techniques are employed to improve the overall SEU immunity of the shift registers. Circuit-level RHBD techniques include dual-interleaving and gated-feedback that achieve SEU mitigation through local latchlevel redundancy and correction. In addition, register-level RHBD based on triple-module redundancy (TMR) versions of dual-interleaved and gated-feedback cell shift registers is also realized to gauge the performance improvement offered by TMR. At the device-level, RHBD C-BE SiGe HBTs with single collector and base contacts and significantly smaller deep trench-enclosed area than standard C-BE -B-C devices with dual collector and base contacts are used to reduce the upset sensitive area. The SEU performance of these shift registers was then tested using heavy ions and standard bit-error testing methods. The results obtained are compared to the unhardened standard shift register designed with CBEBC SiGe HBTs. The RHBD-enhanced shift registers perform significantly better than the unhardened circuit, with the TMR technique proving very effective in achieving significant SEU immunity.

Abstract-A measurement system for internal node testing of integrated circuits using a micromachined photoconductive sampling probe is described and characterized. Special emphasis is placed upon the system performance, demonstrating how absolute voltage measurements are achieved in a dc-to-mm-wave bandwidth. The feasibility of the setup is illustrated using an InP heterojunction bipolar transistor frequency divider. Detailed waveforms at different circuit nodes and the corresponding propagation delays from within this circuit at operating frequencies up to 10 GHz are presented. The results demonstrate for the first time the use of photoconductive probes for calibration-free, absolute-voltage, dc-coupled potential measurements in highfrequency and high-speed integrated circuits.

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