Abstract. Optimization techniques for DSP circuits are described based on the design experience with a number of high-speed digital filter chips. These designs show that efficient high speed digital filter designs can be achieved using several optimizations at the architecture, circuit, and layout level. The problems of automating these optimizations in a general DSP synthesis environment are discussed, and possible CAD solutions are proposed.

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A VLSI implementation of an integrated complete adaptive beamforming processor and QAM demodulator is presented. The adaptive beamforming processor includes variable number of adaptive beamforming channel combining, a fully writable training processor, a programmable adaptive beamforming control processor, and a microcontroller interface. Interleaving area intensive blocks such as the Nyquist filters and multipliers is often employed to save chip area and thus enable the integration of all these features into a single chip. This chip can operate as a stand-alone adaptive beamforming QAM demodulator, or it can work together with an adaptive equalizer for the high bit-rate indoor wireless applications. In a 2.22 dB SINR interference environment, the receiver achieves a link quality of 32.6 dB SNR by the digital adaptive beamforming processing.