When the flip-chip packaging has been moving to the lead-free, fine-pitch and high-current-density packaging, the flip chip with copper-pillar-bump interconnects can provide a solution to this need. However, this package during the thermal cycling test (TCT) still suffers the reliability problems such as delamination at the Cu low-k materials or at the interface between the UBM (under bump metallurgy) and aluminum pad.The purpose of this study is to measure and calculate thermallyinduced deformations and stresses of flip-chip ball grid array (BGA) packages with a copper-pillar-bump interconnected chip inside. In the experiments, full-field Twyman-Green and moiré interferometries are used to measure out-of-plane deformations on the chip surfaces of the package during a heating process and inplane deformations on the cross-section surface of the package under a specific thermal loading, respectively. A finite element method (FEM) and Suhir's die-attachment assembly theory being validated by experimental data are employed to analyze the thermally-induced deformations and stresses of the package to gain insight into their mechanics. The experimental results show the zero-warpage temperature (or zero-stress temperatures) for this package is 115 due to the Tg of the underfill material rather than its curing temperature. It is also found that the thermal deformations of the package calculated by FEM and theory are well consistent with Twyman-Green and moiré results. Furthermore, the local stresses around the critical copper-pillar bump joint region (especially at aluminum pad and low-k layer) where the possible failures occur during the TCT are investigated in detail through the validated FEM model. The results indicate that die/substrate thickness ratio would have significant effect on the stresses at aluminum pad and low-k layer, as well as package warpage and die stress.

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Through Silicon Interposer (TSI) needs to fulfill multi-die stacking in one packaging which can bring high integration density, short interconnection length and small size for next generation devices. Die stacking is a key process in the TSI manufacturing flow, and within that process, die warpage is of central concern. This is because the large warpage of the Si-interposer induces poor joining of μ-bump interconnection, lithograph missing and die breakage during the assembly process. According to our experience, the Cu metal density of redistribution layer (RDL) significantly effects on TSI warpage.[2] The work proposes to design four different Cu metal densities, namely code A (10~25%), B (25~40%), C (40~55%) and D (55~70%) and combine the different metal density to investigate the relationship between Cu metal pattern density and TSI warpage under four different TSI size. Each unit of Cu metal density area is 12 x 12 mm 2 . The TSI size is ranging from unit 1 x 1 (12 x 12 mm 2 ), 1 x 2 (12 x 24 mm 2 ), 2 x 2 (24 x 24 mm 2 ) and 2 x 3 (24 x 36 mm 2 ).In this work, the TSI warpage modeling methodology has been developed and carried out to find the correlation between pattern density and warpage behavior using the finite element method (FEM).A simplified pattern-inclusion model has been constructed to obtain its warpage response under a thermal loading. Furthermore, the equivalent model has been established to obtain the effective mechanical properties of the equivalent layer (i.e., the composite layer of Cu traces and IMD) through adapting the warpage results to correctly match the simplified pattern-inclusion model. Therefore, the TSI warpage can be calculated during the reflow process after acquiring the effective mechanical properties of different Cu pattern densities. The simulation warpage variation of 1 x 1 (12 x 12 mm 2 ) TSI die size for code A, B, C and D are 8 μm, 19 μm, 32 μm, and 47 μm, respectively. The simulation results indicate that large TSI with high Cu metal density possesses high warpage.After fabricating the different Cu metal density wafer, the wafer was grinded to 100 μm for dicing, then using thermal shadow moiré to measure the TSI warpage after one time reflow process. The experimental TSI warpage variation of 1 x 1 (12 x 12 mm 2 ) TSI die size with code A, B, C and D are 6~10 μm, 21~26 μm, 31~36 μm, and 43~70 μm, respectively. The experimental results imply that large TSI with high Cu metal density possesses high warpage. After measuring the warpage of those dies during the thermal curve, we compared the measurement data with our simulation result and explored 3 subjects: different pattern density, die size, and symmetry. We found the TSI warpage between simulation and measurement result are consistent. The finite element simulation results in the work correlate well with the experimental test results. Therefore, we are highly confident that this finite element model can help generate design guidelines for wafer patterns and predict the die warpage variation during the assembly process....

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Advanced wafer technology node has moved forward to 40 nm and below with an ultra low-K (ULK) dielectric constant value of 2.5. ULK shows lower mechanical strength and poor adhesion than that of low-K dielectric. Cu/ULK delamination becomes the major concern during the packaging reliability test. After eliminating the Cu/low-K delamination issue, experimental result shows that die crack become another major failure in 40 nm flip chip packaging reliability test after the temperature cycling test (TCT). The die crack failure can be detected by C-mode scanning acoustic microscopy (CSAM). CSAM image shows a crescent moon shape die crack. The scanning electron microscopy (SEM) cross-section image shows the crack was initialed from the underfill fillet upper part edge and penetrated to the die sidewall, then propagated toward to the active circuit side. Finite element simulation result shows that the die crack failure should initial from the die backside edge. The die crack was occurred by two mechanisms. The first is the bending stress at the die backside, which resulted by the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate. The second is the thermo-mechanical stress, which resulted by the local CTE mismatch between the silicon die and the underfill. Simulation parametric study shows that with low underfill fillet height and smaller fillet tip angle can reduce the thermo-mechanical stress. Besides, this work attaches a one-piece heat sink on the die to increase the packaging stiffness to resist the bending stress induced by the substrate shrinkage. This work verifies the two proposed solutions using the packaging TCT experiment. Experimental results demonstrate to lower the underfill fillet height, reduce the fillet tip angle or attach a heat sink on a flip-chip die are the effective way to solve the die crack issue.