Cu pillar bump-on-trace (BoT) design for ultra low-k packaging

Chen, K. M.; Wu, C. Y.; Chou, H. L.; Kuo, Ping‐Huan

doi:10.1109/impact.2013.6706666

Cited by 3 publications

(1 citation statement)

References 7 publications

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“…The Cu pillar bump consists of thick plated copper post and solder cap, the solder volume in the solder cap is much smaller than the solder bump. Due to this structure, the Cu pillar bump can get finer pitch and better electromigration performance, and being compatible with the bump-on-trace (BOT) process which is for low cost and small form-factor application [6][7][8][9]. The Cu pillar bump has much better performance, but it induces higher stress in the chip side, as the Cu has much higher modulus which add the constraint for the displacement caused by coefficient of thermal expansion (CTE) mismatch between the Si chip and organic substrate [10,11].…”

Section: Introductionmentioning

confidence: 99%

Design Optimization of Pillar Bump Structure for Minimizing the Stress in Brittle Low K Dielectric Material Layer

Long

Shang

Zhang

2019

Acta Metall. Sin. (Engl. Lett.)

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Cu pillar bump offers a number of advantages for flip chip packaging, compared to the conventional solder bump. However, due to its rigidity structure, Cu pillar bump introduces a lot of stress to the chip, which causes the failure of packaging structures, especially for the advanced node devices which typically have brittle low K dielectric material. In this paper, for the first time we propose two types of Cu pillar structures to reduce the stress. The first Cu pillar structure has bigger Cu dimensions at the base. The other one is designed to add an additional Cu pad under the Cu pillar bump. Finite element analysis is used to study the stress of the both structures, and it is found that with the increase in pillar bump contact area over the chip surface, the stress decreases in both structures. Results also indicate that the Cu pillar bump undercut induces higher stress, and thin Cu 6 Sn 5 intermetallic compound has less impact on the stress during flip chip mount reflow. The study provides a novel way to improve the reliability by reducing the stress in the Cu pillar bump related packaging.

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