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IIi is optimized price/performance and ease of use for the system designer. Stated differently, the CPU must deliver a lot of performance for the least impact on overall system cost and also enable simplified system design. An important strategy in enabling low-cost SPARC-based systems is to leverage the PC industry economy of scale by using the industry-standard PCI I/O bus. The integrated 66-MHz PCI interface gives the Ultra-SPARC-IIi access to cost-efficient PC graphics accelerators as well as other I/O cards. Since the CPU also contains an interface to Sun's proprietary high-speed UPA64 bus, our own high-end graphics accelerators such as Creator3D can be used. A CPU in the desktop arena must strike the "sweetspot" in a multidimensional battle of conflicting design objectives: highperformance, controlled power consumption, low cost, quick time to market, and a capability for simplified system design. The net result of a system containing an UltraSPARC-IIi will realize a substantial cost savings. More functionality is on the die, and as a result, there are fewer system components; reduced board-level routing, layers, and complexity; and system-level power consumption. Integration attacks overall system cost, but integrating too much or the wrong type of functionality can become counterproductive. Absolute performance is also obviously important, but we attempt to achieve the knee of the cost/performance curve. We wanted to avoid reaching the point where exorbitant area and complexity is required to gain that last 5% of performance. The resulting CPU from this delicate balancing act of simultaneously optimizing many different objectives is an efficient machine capable of taking SPARC into new markets while solidly preserving those that already exist.

Abstract. This paper presents an innovative tool used during the verification of the UltraSPARC #IIIi (TM) processor. UltraSparc #IIIi operates in a multi-processor environment. Verifying the robustness of the cache coherency maintaining parts of the design was one of the main challenges facing the functional verification team. The team adopted a combination of standard, "classic" techniques and methodologies, as well as some new innovative approaches. This mixture of old and new led to a well-balanced, robust verification flow which enabled finding the majority of the design problems (bugs) early in the pre-silicon stage of the project. This paper discusses an internal tool (Sniper) (patent pending) which increases the processor bus activity in a way which would uncover subtle coherency problems. Architecture OverviewThe UltraSPARC #IIIi processor is a third generation 64b 4-instruction issue SPARC(TM) RISC processor which supports high-end desktop workstations and workgroup servers with focus on higher system integration and cost reduction. The chip operates at 1.1GHz to 1.4GHz. The processor core uses a 14-stage pipeline described in [1,2,3] that supports the concurrent launch of up to six instructions which can consist of 2 integer operations, 2 floating point operations, 1 memory operation and 1 control transfer instruction.[5] On-chip, level 1 caches include 64KB 4-way data cache, a 32KB 4-way instruction cache, a 2KB 4-way data prefetch cache, and a 2KB 4-way write cache. The instruction and data caches have data parity protection. The design includes a 1MB on-chip, (64B line size) level 2 cache that is used for both instruction and data caching. It implements a pseudo-random cache line replacement algorithm. The level 2 cache is a writeback, write-allocate cache, supporting the MOESI coherency protocol.[5] The proprietary 200MHz, 128 bit system interface (JBUS) enables processors and other bus agents to communicate via the shared address and data bus with 3.2GB/s maximum bandwidth.[5] The on-chip memory controller