UltraSPARC-II/: expanding the boundaries of a system on a chip

Normoyle, K.; Csoppenszky, M.A.; Tzeng, A.; Johnson, Timothy; Furman, C.; Mostoufi, J.

doi:10.1109/40.671399

Cited by 13 publications

(3 citation statements)

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“…Another approach based on confidence estimation ] shows good reduction in performance penalty, but the power savings are much lower than that of a conventional filter cache. Fetch prediction has been used in Rotenberg et al [1996], Normoyle et al [1998], andKessler [1999]. It exploits the fact that many branches tend to favor one outcome and the same control path may be taken repeatedly.…”

Section: Background and Related Workmentioning

confidence: 99%

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A predictive decode filter cache for reducing power consumption in embedded processors

Tang

Kejariwal

Veidenbaum

et al. 2007

ACM Trans. Des. Autom. Electron. Syst.

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With advances in semiconductor technology, power management has increasingly become a very important design constraint in processor design. In embedded processors, instruction fetch and decode consume more than 40% of processor power. This calls for development of power minimization techniques for the fetch and decode stages of the processor pipeline. For this, filter cache has been proposed as an architectural extension for reducing the power consumption. A filter cache is placed between the CPU and the instruction cache (I-cache) to provide the instruction stream. A filter cache has the advantages of shorter access time and lower power consumption. However, the downside of a filter cache is a possible performance loss in case of cache misses.In this article, we present a novel technique-decode filter cache (DFC)-for minimizing power consumption with minimal performance impact. The DFC stores decoded instructions. Thus, a hit in the DFC eliminates instruction fetch and its subsequent decoding. The bypassing of both instruction fetch and decode reduces processor power. We present a runtime approach for predicting whether the next fetch source is present in the DFC. In case a miss is predicted, we reduce the miss penalty by accessing the I-cache directly. We propose to classify instructions as cacheable or noncacheable, depending on the decode width. For efficient use of the cache space, a sectored cache design is used for the DFC so that both cacheable and noncacheable instructions can coexist in the DFC sector. Experimental results show that the DFC reduces processor power by 34% on an average and our next fetch prediction mechanism reduces miss penalty by more than 91%.

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Section: Background and Related Workmentioning

confidence: 99%

“…It exploits the fact that many branches tend to favor one outcome and the same control path may be taken repeatedly. In Alpha 21264 [Kessler 1999] and UltraSparc II [Normoyle et al 1998], each line in the I-cache has the following format: (tag, data, line-prediction, way-prediction).…”

Section: Background and Related Workmentioning

confidence: 99%

A predictive decode filter cache for reducing power consumption in embedded processors

Tang

Kejariwal

Veidenbaum

et al. 2007

ACM Trans. Des. Autom. Electron. Syst.

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“…Running on a 440 MHz UltraSPARC-IIi [6] based Sun Ultra-10 workstation, this simulator takes approximately 4.5 hours to evaluate a billion instructions. If a designer had to evaluate 2000 architecture configurations with 8 application runs of a billion instructions each, it would take over 8.21 years to complete all the simulations serially.…”

Section: Introductionmentioning

confidence: 99%

An instruction throughput model of superscalar processors

Taha

Wills

14th IEEE International Workshop on Rapid Systems Prototyping, 2003. Proceedings.

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With advances in semiconductor technology, processors are becoming larger and more complex. Future processor designers will face an enormous design space, and must evaluate more architecture design points to reach a final optimum design. This exploration is currently performed using cycle accurate simulators that are accurate but slow, limiting a comprehensive search of design options. The vast design space and time to market economic pressures motivate the need for faster architectural evaluation methods.The model presented in this paper facilitates a rapid exploration of the architecture design space for superscalar processors. It supplements current design tools by narrowing a large design space quickly, after which existing cycle accurate simulators can arrive at a precise optimum design. This allows a designer to select the final architecture design much faster than with traditional tools. The model calculates the instruction throughput of superscalar processors using a set of key architecture and application properties. It was validated with the Simplescalar out-of-order simulator. Results were within 5.5% accuracy of the cycle accurate simulator, but executed 40,000 times faster.

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