A predictive decode filter cache for reducing power consumption in embedded processors

Abstract

With advances in semiconductor technology, power management has increasingly become a very important design constraint in processor design. In embedded processors, instruction fetch and decode consume more than 40% of processor power. This calls for development of power minimization techniques for the fetch and decode stages of the processor pipeline. For this, filter cache has been proposed as an architectural extension for reducing the power consumption. A filter cache is placed between the CPU and the instruction cache (I-cache) to provide the instruction stream. A filter cache has the advantages of shorter access time and lower power consumption. However, the downside of a filter cache is a possible performance loss in case of cache misses.In this article, we present a novel technique-decode filter cache (DFC)-for minimizing power consumption with minimal performance impact. The DFC stores decoded instructions. Thus, a hit in the DFC eliminates instruction fetch and its subsequent decoding. The bypassing of both instruction fetch and decode reduces processor power. We present a runtime approach for predicting whether the next fetch source is present in the DFC. In case a miss is predicted, we reduce the miss penalty by accessing the I-cache directly. We propose to classify instructions as cacheable or noncacheable, depending on the decode width. For efficient use of the cache space, a sectored cache design is used for the DFC so that both cacheable and noncacheable instructions can coexist in the DFC sector. Experimental results show that the DFC reduces processor power by 34% on an average and our next fetch prediction mechanism reduces miss penalty by more than 91%.

Reducing Leakage through Filter Cache

“…The hierarchy is very simple, more than other structures proposed in literature. It does not have any particular promoting mechanism between L1 and L0 [17] or prediction mechanism [18]. "Conventional" leakage-saving techniques (Figure 3-a) can select the lines to put into low-power state by using many different policies [7,19,20].…”

Data Filter Cache with Partial Tag Matching for Low Power Embedded Processor

“…Because the performance degradation may not be acceptable in modern high-performance embedded environments, researchers have studied ways of addressing this weakness [4]- [6]. These studies have focused on mitigating miss penalty of filter cache or increasing the hit rate of filter cache.…”

“…In order to reduce miss penalty of the filter cache, a predictive filter cache has been proposed [4]. In this structure, a predictor is added to the filter cache system and the predictor selects the access path between L1 cache and filter cache.…”