Selective Access to Filter Cache for Low-Power Embedded Systems

Kwak, Jong Wook; Choi, Ju Hee

doi:10.1109/hicss.2010.330

Cited by 5 publications

(1 citation statement)

References 20 publications

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“…Microarchitectural techniques for saving energy in specific components e.g. main memory ( [82][83][84]), cache [6,16,35,[85][86][87][88][89][90][91][92][93][94][95][96][97][98][99][100][101][102][103], scratchpad memory [104], TLB [105] or making other changes to memory hierarchy e.g. adding extra components [106,107].…”

Section: Overviewmentioning

confidence: 99%

A survey of techniques for improving energy efficiency in embedded computing systems

Mittal¹

2014

IJCAET

135

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Recent technological advances have greatly improved the performance and features of embedded systems. With the number of just mobile devices now reaching nearly equal to the population of earth, embedded systems have truly become ubiquitous. These trends, however, have also made the task of managing their power consumption extremely challenging. In recent years, several techniques have been proposed to address this issue. In this paper, we survey the techniques for managing power consumption of embedded systems. We discuss the need of power management and provide a classification of the techniques on several important parameters to highlight their similarities and differences. This paper is intended to help the researchers and application-developers in gaining insights into the working of power management techniques and designing even more efficient high-performance embedded systems of tomorrow.

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Section: Overviewmentioning

confidence: 99%

A survey of techniques for improving energy efficiency in embedded computing systems

Mittal¹

2014

IJCAET

135

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Multi objective design space exploration of cache for embedded applications

Alipour¹,

Taghdisi

Sadeghzadeh

2012

2012 25th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)

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High contribution of cache access power in the total power consumption of embedded processors has made it a major concern in embedded system designs. By technology scaling, leakage power has created more stress on design constraint and power budget of embedded processors. Therefore; designers require a comprehensive design space exploration of cache architecture. In this paper we find out the optimum performance per power consumption points for cache sizes based on design space exploration using a new energy model considering dynamic and leakage energy of cache for embedded applications. Full exploration is performed based on different feature sizes to find out the effect of technology scale down on power parameters of cache. Results show that in different feature sizes 30% of static power and 43 % of total power of an embedded core is consumed in the cache hierarchy in average. It means based on this work in smaller feature sizes and for embedded application that can tolerate performance lose up to 3%, we should select smaller cache hierarchy to deliver better performance per power as the most important parameter in designing embedded systems.

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Cache power and performance tradeoffs for embedded applications

Alipour

Salehi

Moshari

2011

2011 IEEE International Conference on Computer Applications and Industrial Electronics (ICCAIE)

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As embedded applications have became more complex, design of embedded processors has created a research area for low power and yet high performance architectures. Power consumption is as important as performance in battery-powered embedded systems and in future, embedded processors are to process more computationintensive applications with limited power budgets. Therefore, power consumption of theses processors will become more critical. According to the high contribution of memory access power in total power consumption of embedded systems, memory architecture of embedded systems strongly influences the system design objectives. Cache memories are usually used to improve the performance and power consumption by bridging the gap between the speed and power consumption of the main memory and CPU, therefore, the system performance and power consumption is severely related to the average memory access time and power consumption which makes the cache architecture as a major concern in designing embedded processors. Therefore, the embedded system designer requires a comprehensive design space exploration for memory architecture. In this paper we explore the design space of cache in embedded processors to find out the cache sizes which have the optimum performance/power consumption in embedded applications.

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Selective Access to Filter Cache for Low-Power Embedded Systems

Cited by 5 publications

References 20 publications

A survey of techniques for improving energy efficiency in embedded computing systems

A survey of techniques for improving energy efficiency in embedded computing systems

Multi objective design space exploration of cache for embedded applications

Cache power and performance tradeoffs for embedded applications

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