Cache power and performance tradeoffs for embedded applications

Abstract

As embedded applications have became more complex, design of embedded processors has created a research area for low power and yet high performance architectures. Power consumption is as important as performance in battery-powered embedded systems and in future, embedded processors are to process more computationintensive applications with limited power budgets. Therefore, power consumption of theses processors will become more critical. According to the high contribution of memory access power in total power consumption of embedded systems, memory architecture of embedded systems strongly influences the system design objectives. Cache memories are usually used to improve the performance and power consumption by bridging the gap between the speed and power consumption of the main memory and CPU, therefore, the system performance and power consumption is severely related to the average memory access time and power consumption which makes the cache architecture as a major concern in designing embedded processors. Therefore, the embedded system designer requires a comprehensive design space exploration for memory architecture. In this paper we explore the design space of cache in embedded processors to find out the cache sizes which have the optimum performance/power consumption in embedded applications.

Multi objective design space exploration of cache for embedded applications

“…We have calculated the energy consumption of each cache configuration (dynamic and total separately) by using the proposed model of [23] which considers the effect of all parameters i.e. number of cache misses/hits, access time of cache, cache level, type of accesses (read or write), and static/ dynamic energy on the energy dissipation of the cache.…”

“…Exploration of [20] reduced 300 cache configurations to 36 configurations (6 sizes for L1 and 6 sizes for L2). In this paper we make more reduction on cache size configurations, by considering both dynamic and static power consumption of each configuration using the cache power model introduced in [23]. The proposed exploration in [20] has calculated the best cache size for each application based on performance.…”

“…We used the proposed model of [23]. They have used CACTI 5.0 [18], a tool from HP that is a platform for extracting parameters relevant to cache size considering fabrication technology.…”

A survey of techniques for improving energy efficiency in embedded computing systems

“…Microarchitectural techniques for saving energy in specific components e.g. main memory ( [82][83][84]), cache [6,16,35,[85][86][87][88][89][90][91][92][93][94][95][96][97][98][99][100][101][102][103], scratchpad memory [104], TLB [105] or making other changes to memory hierarchy e.g. adding extra components [106,107].…”