No abstract

Inthis paper, we propose a code based technique, Variable-to-Fixed (V -F) coding, for power efficient test data compression. The proposed scheme with the aim of achieving high compression ratio and low power consumption relies on reducing, the number of bits for representing the original test vector and the number of transitions per second. Simulation results on ISCAS'89 benchmark circuits, demonstrate that this optimization methodology helps achieve reduced test data volume than previous schemes for cases where the number of specified bits in the test set is relatively few.

This paper presents a video compression system using wavelet lifting scheme. Video compression algorithms (“codecs”) manipulate video signals to dramatically reduce the storage and bandwidth required while maximizing the perceived video quality. There are four common methods for compression; discrete cosine transforms (DCT), vector quantization (VQ), fractal compression, and discrete wavelet transform (DWT). A gradient based motion estimation algorithm based on shapemotion prediction is used which takes advantage of the correlation between neighboring Binary Alpha Blocks (BABs), to match with the MPEG-4 shape coding case and speed up the estimation process. Then a non-redundant wavelet transform has been implemented as an iterative filter banks with down sampling operations. LSK operates without lists and is suitable for a fast, simple hardware implementation. Here the Set Partitioned Embedded bloCK coder (SPECK) image compression called Improved Listless SPECK (ILSPECK) is used. ILSPECK code a single zero to several insignificant subbands. This reduces the length of the output bit string as well as encoding/decoding time.

Ìn this paper, we propose two code based techniques: Variable-to-Fixed codes and Fixed-to-Variable codes for power efficient test data compression. The proposed scheme with the aim of achieving high compression ratio and low power consumption relies on reducing, the number of bits for representing the original test vector and the number of transitions per second. Simulation results on ISCAS"89 benchmarks demonstrate that this optimization methodology helps achieve reduced test data volume and power than previous schemes for cases where the number of specified bits in the test set is relatively few.

One of the major challenges in testing a system-on-a-chip (SoC