No abstract

No abstract

A novel mixed analogue/digital design of a phase picking algorithm in an oversampling clock phase recovery is presented. The proposed approach results in reduced processing time, improved integrability with analogue front-end and low noise generation. Simulations of a 10 Gbit/s burst-mode clock phase alignment circuit in a 0.25 mm SiGe BiCMOS process, show a simulated processing delay of only 280 ps.

Abstract-This paper describes a compact, low cost, low power vector network analyzer. The instrument's measurement range spans from 300 kHz up to 1500 MHz. The design was conceived to make the instrument generic and suited for many application areas. The instrument runs a local web server, hosting a java applet that contains application specific data processing software. We present the system architecture, discuss sub-block performance and propose some possible applications.

No abstract