High efficiency Cu2ZnSnS4 solar cells have been fabricated on glass substrates by thermal evaporation of Cu, Zn, Sn, and S. Solar cells with up to 6.8% efficiency were obtained with absorber layer thicknesses less than 1 μm and annealing times in the minutes. Detailed electrical analysis of the devices indicate that the performance of the devices is limited by high series resistance, a “double diode” behavior of the current voltage characteristics, and an open circuit voltage that is limited by a carrier recombination process with an activation energy below the band gap of the material.

Nano/micro‐wire silicon solar cells, consisting of wire‐arrays of radial p–n junction structures, are expected to offer performance enhancement at lower costs, using smaller volumes of low carrier lifetime, cheaper silicon. Using inexpensive microsphere‐lithography‐based fabrication that is scalable to large areas, we have demonstrated wire‐array solar cells that outperform the control cell. Key to the design of these cells is the impact of various parameters, such as wire diameter and junction depth, that influences the competing effects of light trapping ability of the wire‐array, quantum efficiency, and series resistance of the resulting device. Using capacitance measurements we can identify two possible types of junction structure in a wire‐array solar cell: radial and planar. We show that the former is the prerequisite for performance‐enhancing wire‐array solar cells. Copyright © 2010 John Wiley & Sons, Ltd.