This paper presents a Verilog-A implementation of three different energy efficient architectures of Successive Approximation Register (SAR) analog-to-digital converter (ADC) namely SAR ADC with monotonic capacitor switching DAC, SAR ADC with split-monotonic capacitor switching DAC and SAR ADC with bypass window technique. These architectures were constructed for a resolution of 4 bits. Simulation results of all the three were compared to analyze the convergence of output nodal voltage and the reduction in switching activity. SAR ADC with bypass window technique was observed to be efficient with a switching activity of 3 for a switching activity of 4 in other two architectures. The limitations of this architecture were studied and a new architecture was proposed overcoming the limitations. Verilog-A implementation was carried out for the proposed architecture. From the simulation results it was observed that the proposed architecture retained the functionality of existing architecture except for a specific input combination where the existing architecture was less accurate. Result from the proposed architecture was 90.9% more accurate than the existing architecture.

In existing method separate DC-DC and DC-AC converter topologies are required to supply DC and AC loads in which efficiency is poor. In the proposed work single converter topology of interleaved hybrid converter is used to provide simultaneous AC and DC output. Battery is used to supply load in absence of solar power. Artificial Neural Network control strategy is used to provide gating signals for the converter which improves the overall performance and stability of the system.AC and DC output from the interleaved hybrid converter are obtained using MATLAB/Simulink

In recent years Evolutionary computation has its growth to extent. Synthesis of non-uniform