X-ray diffraction and incoherent inelastic neutron scattering studies are performed to clarify the phase transition mechanism of Cu(HCOO) 2 ·4H 2 O. Contrary to the previous electrical study, we find no evidence of the existence of an intermediate ferrielectric phase. We determine the accurate antiferroelectric structure. It turns out that the atomic arrangement of the Cu(HCOO) 2 layers remains unchanged through the phase transition, while the antiferroelectric H 2 O layers take one of two disordered paraelectric arrangements alternately along the c-axis. We discuss that the rotation of the H 2 O molecules induces the structural correlation one-dimensionally along the antiferroelectric b-axis.

We propose a dynamic voltage boosting (DVB) method for improving performance by slightly boosting voltage within a withstand voltage. We measured an improvement of 44 % voltage drop with about 10 % area overhead in a 65 nm CMOS. This DVB method combined with a series power gating can be used to achieve high performance for low-cost low-power SoCs in advanced process technology. IntroductionAs process technology has scaled down, transistor counts have been rapidly increasing, and an LSI with multi CPUs is now available for consumer use [1]. In these consumer LSIs, the power integrity, which was a major issue in highperformance LSIs, has become a very critical issue. To improve power integrity, a circuit technique that maintains a smaller voltage margin, which is the difference between the lowest and standard operational voltages, is needed for low power multi-processor SoCs. This circuit technology for maintaining a small voltage margin is also a key to low-voltage operation, and thus, it will become more important in the 45 nm process technology generation and beyond.An on-chip voltage drop canceller [2], [3] has been developed that cancels the momentary voltage drop caused by a rush current when a circuit wakes up or by on-chip supply resonance. However, these methods are insufficient for improving performance because the power integrity of future LSIs is too stringent to allow increases in wire resistance and concentration of current flow in a heavy load condition. Therefore, a method for continuously boosting voltage under heavy load conditions is needed for achieving higher operational performance against PVT variation. The key point is how to determine the exact moment when the DVB turns on. An on-chip voltage detector is a key feature for the DVB control as well as to control supply voltage within the withstand voltage.

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