True-time-delays enable wideband analog and hybrid beamforming by mitigating the beam squint problem. This paper reports a true-time-delay beamforming receiver supporting delays up to three carrier-frequency cycles. The implementation is the first published work in which the delays scale with the carrier frequency. The scaling enables true-time-delays for large arrays at low-GHz frequencies where long delays are required due to λc/2 antenna spacing. The delays are implemented through delayed resampling of a passive mixer's discrete-time output. Driving the mixers with pulse-skipped local oscillator (LO) signals allows the delay range to exceed one carrier cycle. A polyphase receiver structure prevents aliasing of noise and unwanted tones caused by LO pulse-skipping. Our prototype implementation demonstrates squint-free beamforming for an 800 MHz instantaneous RF bandwidth. The proposed true-timedelay is efficient for large arrays since the power consumption per antenna is only 5-13 mW across the 0.6-4.0 GHz frequency range. The prototype was implemented in 28-nm FD-SOI CMOS, and the die area including bonding pads is only 1.2 mm 2 .

Analog domain true-time-delays (TTD) are desired in hybrid beamforming receivers with large relative bandwidths to mitigate the problem of beam squint. We propose a true-timedelay beamforming receiver architecture which enables squintfree wideband spatial filtering prior to the A/D conversion. The receiver implements true-time-delay with delayed re-sampling of the discrete-time output of a passive mixer. The receiver has the capability to extend the range of the beamforming delays from one to several carrier periods of the RF signal with pulse-skipped local oscillator (LO) signals, thereby enabling TTD beamforming with large antenna arrays. Further, a polyphase structure with parallel mixers is proposed to prevent spectral aliasing resulting from the lowered sample rate of the pulse-skipped LO signals. In addition, the maximum beamforming delay scales with the LO frequency, supporting large arrays also at low frequencies where the antenna separation set by the wavelength is large. We verify the proposed concepts with transistor-level simulation of the receiver implemented with a 28-nm CMOS process. The design achieves a squint-free beamforming for a 400 MHz RF bandwidth, and a maximum beamforming delay of three carrier time periods. The power consumption for a 3 GHz carrier frequency is 4 mW per antenna.

Spatial diversity advantages such as improved signal-to-noise ratio and in-band blocker filtering can be achieved through beamforming in the digital and/or analog domain. Digital beamforming benefits from the precision and efficient parallelization of digital signal processing. On the other hand, analog beamforming allows the filtering of in-band but out-of-beam blockers before the ADC which can improve the dynamic range performance of the receiver. A delay method based on resampling has recently emerged as a viable solution for enabling true-time-delay analog beamforming receivers, which overcome the fractional bandwidth limitation of phase-shift beamforming due to beam squint. This paper presents a 22-nm CMOS receiver prototype that enables reconfiguration between true-time-delay analog and digital beamforming to allow choosing the more suitable operation mode in different signal environments. The reconfigurability is achieved by exploiting the time-interleaved nature of both the resampling delay setup and high speed ADCs. In addition to the beamforming mode reconfigurability, the receiver achieves stateof-the-art 2 GHz instantaneous beamformed bandwidth in the analog mode. The receiver reaches a 100% fractional bandwidth at the low end of the 1-6 GHz frequency range.INDEX TERMS Analog beamforming, beam squint, CMOS, digital beamforming, integrated circuit, phased array, radio receiver, spatial filtering, true-time-delay.

This paper presents a wideband 8-way timeinterleaved (TI) 9-bit successive approximation register (SAR) analog-to-digital converter (ADC) with overlapping conversion steps that improve the speed of operation. The ADC generates its clocks using a synchronous counter based circuit which reduces the SAR delay. A common-mode reference based split capacitor array digital-to-analog converter (DAC) is implemented that achieves high speed and low power consumption. Simulation results are presented for the ADC designed in a 22 nm CMOS process. The TI ADC achieves at least 7.7 ENOB at 2 GS/s and consumes a total of 19.8 mW from 0.8 V supplies, resulting in 47.6 fF/conv-step. The single ADC achieves 8.34 ENOB at 250 MS/s, consuming 1.43 mW in total and 17.7 fF/conv-step.

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