Constant shrinkage in the device dimensions has resulted in very dense memory cells. The probability of occurrence of multiple bit errors is much higher in very dense memory cells. Conventional Error Correcting Codes (ECC) cannot correct multiple errors in memories even though many of these are capable of detecting multiple errors. This paper presents a novel decoding algorithm to detect and correct multiple errors in memory based on Matrix Codes. The algorithm used is such that it can correct a maximum of eleven errors in a 32-bit data and a maximum of nine errors in a 16-bit data. The proposed method can be used to improve the memory yield in presence of multiple-bit upsets. It can be applied for correcting burst errors wherein, a continuous sequence of data bits are affected when high energetic particles from external radiation strike memory, and cause soft errors. The proposed technique performs better than the previously known technique of error detection and correction using Matrix Codes.

Security of electronic data remains the major concern. The art of encryption to secure the data can beachieved in various levels of abstraction. The choice of the logic style in implementing the securityalgorithms has greater significance, and it can enhance the ability of providing better resistance to sidechannel attacks. The static CMOS logic style is proved to be prone to side channel power attacks. Theexploration of CMOS current mode logic style for resistance against these side channel attacks is discussedin this paper. Various characteristics of the current mode logic styles, which make it suitable for makingDPA resistant circuits are explored. A new methodology of biasing the sleep transistors of (MOS currentmode logic) MCML families is proposed. It uses pass gate transistors for power-gating the circuits. Thepower variations of the proposed circuits are compared against the standard CMOS counterparts. Logicgates such as XOR, NAND and AND gate structures of MCML families and static CMOS are designed andcompared for the ability of side channel resistance. A distributed arrangement of sleep transistors forreducing the static power dissipation in the logic gates is also proposed, designed and analyzed. All thelogic gates in MCML and CMOS were implemented using standard 180 nm CMOS technology employingCadence® EDA tools