We explore the electrical characteristics of TiS 3 nanowire field-effect transistor (FETs), over the wide temperature range from 3 to 350 K. These nanomaterials have a quasi-one-dimensional (1D) crystal structure and exhibit a gate-controlled metal−insulator transition (MIT) in their transfer curves. Their room-temperature mobility is ∼20−30 cm 2 /(V s), 2 orders of magnitude smaller than predicted previously, a result that we explain quantitatively in terms of the influence of polar-optical phonon scattering in these materials. In the insulating state (<∼220 K), the transfer curves exhibit unusual mesoscopic fluctuations and a current suppression near zero bias that is common to charge-density wave (CDW) systems. The fluctuations have a nonmonotonic temperature dependence and wash out at a temperature close to that of the bulk MIT, suggesting they may be a feature of quantum interference in the CDW state. Overall, our results demonstrate that quasi-1D TiS 3 nanostructures represent a viable candidate for FET realization and that their functionality is influenced by complex phenomena.

It has recently been suggested that movement variability directly increases the speed of motor learning. Here we use computational modeling of motor adaptation to show that variability can have a broad range of effects on learning, both negative and positive. Experimentally, we also find contributing and decelerating effects. Lastly, through a meta-analysis of published papers, we verify that across a wide range of experiments, movement variability has no statistical relation with learning rate. While motor learning is a complex process that can be modeled, further research is needed to understand the relative importance of the involved factors.

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Hough Transform has been widely used for straight line detection in low-definition and still images, but it suffers from execution time and resource requirements. Field Programmable Gate Arrays (FPGA) provide a competitive alternative for hardware acceleration to reap tremendous computing performance. In this paper, we propose a novel parallel Hough Transform (PHT) and FPGA architecture-associated framework for real-time straight line detection in high-definition videos. A resource-optimized Canny edge detection method with enhanced non-maximum suppression conditions is presented to suppress most possible false edges and obtain more accurate candidate edge pixels for subsequent accelerated computation. Then, a novel PHT algorithm exploiting spatial angle-level parallelism is proposed to upgrade computational accuracy by improving the minimum computational step. Moreover, the FPGA based multi-level pipelined PHT architecture optimized by spatial parallelism ensures real-time computation for 1,024 × 768 resolution videos without any off-chip memory consumption. This framework is evaluated on ALTERA DE2-115 FPGA evaluation platform at a maximum frequency of 200 MHz, and it can calculate straight line parameters in 15.59 ms on the average for one frame. Qualitative and quantitative evaluation results have validated the system performance regarding data throughput, memory bandwidth, resource, speed and robustness.