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This paper describes the application of lock-in thermography (LIT) for flip-chip package-level failure analysis. LIT successfully detected and localized short failures related to both die/C4 bumps and package defects inside the organic substrate. The detail sample preparation to create short defects at different layers, LIT fault isolation methodology, and case studies performed with LIT are also presented in this paper.

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The shrinking geometries in today’s 3-D integrated circuit (IC) designs generate an urgent need for a variety of tools to isolate failures on advanced semiconductor devices. There has been no single technique that adequately addresses all types of failures with the required fast cycle time. Complex failures that are not resolved by the faster global approaches are best addressed by probing technologies, where waveforms or voltages are measured from node to node. These approaches are time-consuming and usually require detailed understanding of the circuit operation. Global techniques that map the secondary effects of defects have been widely used for as many failures as possible. These secondary effects include thermal emission, photon emission, and circuit operation dependencies on localized heating or carrier generation at a defect site. Each technique addresses some segment of the failure mechanisms, but none is universally effective in itself. The use of thermal emission techniques has waned due to the issues of lower power supply voltages, which result in poor sensitivity for older techniques and decrease in minimum resolved feature sizes.