A new design of stripline transition structures and flip-chip interconnects for high-speed digital communication systems implemented in low-temperature cofired ceramic (LTCC) substrates is presented. Simplified fabrication, suitability for LTCC machining, suitability for integration with other components, and connection to integrated stripline or microstrip interconnects for LTCC multichip modules and system on package make this approach well suited for miniaturized, advanced broadband, and highly integrated multichip ceramic modules. The transition provides excellent signal integrity at high-speed digital data rates up to 28 Gbits/s. Full-wave simulations and experimental results demonstrate a cost-effective solution for a wide frequency range from dc to 30 GHz and beyond. Signal integrity and high-speed digital data rate performances are verified through eye diagram and time-domain reflectometry and time-domain transmissometry measurements over a 10-cm long stripline.Index Terms-Full tape thickness feature, low-temperature cofired ceramic (LTCC) interconnect, multichip module (MCM), quasi-coaxial vertical transition, signal integrity, system on package.

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Thin-film microstrip transmission lines fabricated using a Ti adhesion layer followed by layered Cu, Pt, and Au films are measured to determine tradeoffs between manufacturability issues and microwave performance. Since Ti metal has approximately 25 times the resistance of Cu, and currents in a microstrip line flow mainly at the interface with the substrate where the Ti is located, there is the possibility of increased RF signal losses with this structure. It is found that Ti adhesion layers of ≤200-nm thickness cause minimal loss through 40 GHz on DuPont 9K7 low-temperature cofired ceramic substrates, so there is no significant electrical penalty for employing a metal stackup optimized for mechanical durability. These measurements, together with analysis and simulations suggest this will hold in general as long as the thinner, higher resistance adhesion metal is well below one skin depth in thickness at the operating frequency.

An electronic packaging technology that survives the simulated Venusian surface temperature of 465°C and 96 bar pressure in carbon dioxide (CO2) and nitrogen environments, without the corrosive trace gases, was developed. Alumina ceramic substrates and gold conductors on alumina were evaluated for electrical and mechanical performance. The most promising die-attach materials are thick-film gold and alumina-based ceramic pastes. Alumina, sapphire, silicon, and silicon carbide dies were attached to the alumina substrates using these die-attach materials and exposed to 96 bar pressure in a CO2 environment at 465°C for 244 h. The ceramic die-attach material showed consistent shear strengths before and after the test. An alumina ceramic encapsulation material was also evaluated for thermomechanical stability. The devices on the packaging substrates were encapsulated by a ceramic encapsulation with no significant increase in cracks and voids after the Venusian simulator test. Wire pull strength tests were conducted on the gold bond wire to evaluate mechanical durability before and after the Venusian simulator exposure. The average gold bond wire pull strengths before and after exposure were 5.78 g-F and 4 g-F for 1-mil gold bond wires, respectively, meeting the minimum MIL-STD-885 2011.9 standard. The overall wire bond daisy chain resistance change was .47% after the Venus simulator test, indicating a promising wire bond integrity. A titanium package was fabricated to house the ceramic packaging substrate and a two-level metalized feedthrough was fabricated to provide electrical interfaces to the package.

In this study, low-temperature cofired ceramic (LTCC) and 3D-printed ceramic interposers are designed and fabricated for a double-sided power electronic module. The interposer acts as electrical insulation between two direct-bond copper (DBC) power substrates as well as mechanical support to evenly distribute the weight of the top DBC substrate onto the entire bottom DBC substrate instead of directly onto the bare power semiconductor die. A novel LTCC fabrication process for 14 layers of green tapes with premachined recesses and holes is developed. A similar interposer is 3D printed using a ceramic resin. Finally, the fabricated LTCC and 3D-printed interposers are compared.