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In microelectronics there is a continuous trend for devices of higher integration and improved heat dissipation. For the manufacture of ceramic based microelectronic devices the following technologies can be applied. Thick-film hybrid technology uses sintered ceramic substrates, mostly Al2O3, which are screen printed with functional pastes, followed by firing at 850 °C. Alumina substrates provide very good heat conductivity (25 W/mK), but there are only two sides to carry a metallization. An improved miniaturization can be accomplished by multilayer systems using the LTCC technology. LTCC devices are manufactured by screen-printing, stacking and lamination of ceramic green tapes, followed by co-firing. A drawback of LTCCs is their low heat conductivity (3 W/mK) due to their high glass content. By combining hybrid and LTCC technology the advantages of both methods like good thermal conductivity and high multilayer integration, can be joined. Because the failure rate is too high to laminate green tapes on sintered ceramic substrates via thermo compression, Cold Low Pressure Lamination (CLPL) has been used as an alternative lamination process. CLPL is a lamination method, where the joining of the components is performed at room temperature by application of very low pressure (<5 MPa) by using a double sided adhesive tape. During heat treatment the adhesive film keeps the tapes together until the adhesive is completely decomposed; during further temperature increase the tapes are joined by sintering. The paper describes the materials used and processing steps to join the sintered material with the green tapes and discusses effects which occur during firing. These effects like edge curl and crack formation are mainly due to stresses which occur during constrained sintering. Their control can be influenced by changing process parameters.

In this study, laminates consisting of sintered alumina substrates and green Low Temperature Co-fired Ceramics (LTCC) tapes have been produced via Cold Low Pressure Lamination which is based on adhesive tapes for joining of layers at room temperature and pressures <5 MPa. The influences of lamination parameters such as temperature, pressure, and time on the quality of the green and sintered multilayer stack have been determined. If the bottom LTCC layer of an alumina-LTCC-LTCC laminate is metallized by screen printing defects such as crack formation can occur due to stress formation caused by constrained sintering. By adapting the lamination parameters, these stresses can be avoided. Another defect observed is cavities which form along the printed circuit lines. This type of defect is caused by the shrinkage of the circuit line width during firing; by reducing the height of the conductor line during screen printing, the cavity size can be reduced. In addition, different screen-printed metallization layouts have been tested to determine the influence of line and spaces on the quality of sintered laminates.

Hybrid-thick-film circuits consist of many different components, like screen-printed passive elements (conductors, resistors, and electrical vias), SMDs, and active elements like transistors or ICs. Whereas most of passive components are well investigated and described, the electrical vias often remain unattended. Resistive heating caused by high current pulses might lead to the destruction of the vias. In previous work, we set up a 3d FEM model and investigated the influence of non-radial-symmetric contacting and geometric irregularities of the vias on the occurring maximum temperatures. The present contribution deals with the modeling of a failure mechanism of an electrical via caused by high current pulses. When the local temperature exceeds a defined melting temperature, the metallization layer melts and is not available for conduction any more. The current density rises as a consequence of the decreased cross section area of the vias and leads to a higher heat production in a smaller area. This conducts further melting of the metallization layer and results in a positive feedback that accelerates the destruction of the via. The approach of this contribution is to model the described failure mechanism in a 2d-radial-symmetric FEM model. The modeling results were validated using high current measurements of electrical vias. Modeling and measurement of the voltage drop during a constant current pulse agree very well, from very low current density pulses up to pulses that lead to the destruction of the vias.