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The aim of this paper is to show how the Hodgkin-Huxley model of the neuron's membrane potential can be extended to a stochastic one. This extension can be done either by adding fluctuations to the equations of the model or by using Markov kinetic schemes' formalism. We are presenting a new extension of the model. This modification simplifies computational complexity of the neuron model especially when considering a hardware implementation. The hardware implementation of the extended model as a system on a chip using a field-programmable gate array (FPGA) is demonstrated in this paper. The results confirm the reliability of the extended model presented here.

The purpose of this work is to speed up simulations of neural tissues based on the stochastic version of the Hodgkin-Huxley model. Authors achieve that by introducing the system providing random values with desired distribution in simulation process. System consists of two parts. The first one is a high entropy fast parallel random number generator consisting of a hardware true random number generator and graphics processing unit implementation of pseudorandom generation algorithm. The second part of the system is Gaussian distribution approximation algorithm based on a set of generators of uniform distribution. Authors present hardware implementation details of the system, test results of the mentioned parts separately and of the whole system in neural cell simulation task.

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This paper presents a new distance calculation circuit (DCC) that in artificial neural networks is used to calculate distances between vectors of signals. The proposed circuit is a digital, fully parallel and asynchronous solution. The complexity of the circuit strongly depends on the type of the distance measure. Considering two popular measures i.e. the Euclidean (L2) and the Manhattan (L1) one, it is shown that in the L2 case the number of transistors is even ten times larger than in the L1 case. Investigations carried out on the system level show that the L1 measure is a good estimate of the L2 one. For the L1 measure, for an example case of 4 inputs, for 10 bits of resolution of the signals, the number of transistors is equal to c. 2500. As transistors of minimum sizes can be used, the chip area of a single DCC, if realized in the CMOS 180 nm technology, is less than 0.015 mm2.