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The increasing gap between design productivity and chip complexity, and emerging systems-on-achip (SoC) have led to the wide utilization of reusable intellectual property (IP) cores. Educators' responsibility is to provide future generations of SoC architects with knowledge necessary for successful design and use of IP cores, and to offer them a system perspective including both hardware and software. One such proposal is to design an accelerometer IP core for advanced control applications such as robust motion control, servomotor or robotic applications. There are a lot of strong demands on motion control systems, with reasonable resolution and accuracy. The performance of such motion control systems can be greatly enhanced by including some form of velocity or acceleration feedback. An accurate and rapid velocity measurement is vital for high-performance acceleration control. The functionality of the system core is coded in Verilog HDL, mapped onto architecture, simulated, synthesized and implemented on FPGA and tested. The performance evaluation and validation of the developed core can also be done by comparison with a software model realized using Matlab Simulink. The velocity estimates of RTL model can be further improved by considering some factors affecting accuracy, resolution and range of velocity measurements. This validated velocity signals are used to compute the acceleration of the moving object using simple differentiation technique without accumulated quantization errors.